Replace the open-coded tests of K_USER in a thread's user_options with
k_thread_is_user_thread(), and drop the private is_user() helper in
thread.c, which did the same thing. No functional change.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Pair the ARC range operations' arch_irq_lock() with arch_irq_unlock()
to avoid decrementing an outer SMP global lock. Use local IRQ locking
for the all-cache operations too; shared SLC locking is unchanged.
Pair irq_lock() with irq_unlock() in the ESP32 USB serial callback to
balance its SMP global lock state.
Signed-off-by: Jinming Zhao <jinmzhao@qti.qualcomm.com>
arc_core_mpu_remove_mem_partition() disabled the region at
base_region + partition_id, counting upward from the domain-partition
base region, while arc_core_mpu_configure_mem_domain() assigns array
slots counting downward (partitions[i] -> region base - i) and, since
the hole-skip fix, skips zero-sized entries. The two disagree even
without holes, so the wrong region would be disabled if the function
were ever wired up.
Derive the region slot from the partition's array position: count the
valid partitions before partition_id and subtract from the base region,
matching how the configure loop programs them. No-op on holes and
out-of-range ids.
The function has no in-tree callers today; this aligns it with the
configure-side mapping so it is correct if it is ever used.
Fixes: #116321
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
k_mem_domain_remove_partition() zeroes a partition slot in place and
decrements num_partitions, leaving a hole in partitions[]. The ARC MPU
domain region programming loops bounded their iteration with
num_partitions, so each hole consumed one iteration and any valid
partition behind it was never programmed into the MPU, faulting
user-mode accesses with EV_ProtV.
Scan the whole partitions array (bounded by
CONFIG_MAX_DOMAIN_PARTITIONS, since num_partitions no longer reflects
the number of slots to inspect) and program only the non-zero-sized
entries, decrementing the remaining-partition counter only for valid
ones. This matches the arm32 implementation in arm_core_mpu.c and is
applied in:
- arc_core_mpu_configure_mem_domain() (MPU v2/v3/v6, common header)
- arc_core_mpu_configure_thread() gap-filling path (MPU v4/v8)
- arc_core_mpu_configure_mem_domain() non-gap-filling path (MPU v4/v8)
- arc_core_mpu_remove_mem_domain() (MPU v4/v8)
Fixes: #116321
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
A component should not rely on the API it is implementing.
In this case, the arch layer is implementing the arch cache API
(include/zephyr/arch/cache.h), that is used by the public sys cache
API (include/zephyr/cache.h), so it can't call the latter.
Also rework init_dcache_line_size logic since now
CONFIG_DCACHE_LINE_SIZE is always defined even if DCache line size
runtime detection is available.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Across the tree, I/DCACHE_LINE_SIZE is required at compile-time for
macros, compiler attributes, & linker scripts to function correctly
even if run-time cache line detection is available.
So remove the dependency of ICACHE_LINE_SIZE on
ICACHE_LINE_SIZE_DETECT=n, and of DCACHE_LINE_SIZE on
DCACHE_LINE_SIZE_DETECT=n.
DCACHE_LINE_SIZE_DETECT & ICACHE_LINE_SIZE_DETECT Kconfig options
enable querying some SoC register for finding the i/d-cache line size
at the expense of taking more memory and code and a slightly
increased boot time.
Add new hidden options D/ICACHE_LINE_SIZE_DETECT_SUPPORT only selected
by the software component (arch/SoC layer, driver) implementing the system
cache API.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
MWDT does not honor memory orders on __atomic_* or emit fences for
__sync_synchronize() / __atomic_thread_fence(). Route ARC HS MWDT builds
through ARC_MWDT_MEM_ORDERING_WORKAROUND, which selects arch atomics and
barriers implemented in atomic_arc.h and barrier.h.
GCC ARC builds keep ATOMIC_OPERATIONS_BUILTIN and
BARRIER_OPERATIONS_BUILTIN. Revert when MWDT fixes ordering in the
toolchain/runtime.
Signed-off-by: Mohamed Moawad <melhosar@gfoundries.com>
Add memory ordering around the arc_cpu_wake_flag / arc_cpu_sp protocol
used when arch_cpu_start() brings up secondary cores.
The primary must publish _curr_cpu[], arc_cpu_init[], and arc_cpu_sp
before the wake flag is visible, and must not reuse arc_cpu_sp until
the secondary acknowledges. The secondary must not load sp until it
has observed its wake flag, and must complete that load before
clearing the flag.
Use barrier_dmem_fence_full() in arch_cpu_start() and dmb 1 / dmb 3
in the secondary wait path in reset.S.
Signed-off-by: Mohamed Moawad <melhosar@gfoundries.com>
Ensure callee-saved context stores are globally visible before
switch_handle is published on SMP. Other cores poll switch_handle in
z_sched_switch_spin() and may restore context immediately; ARC
store buffering can otherwise expose the publish too early.
Add "dmb 2" in _store_old_thread_callee_regs and fault_s.S.
Signed-off-by: Mohamed Moawad <melhosar@gfoundries.com>
When a device using a second or third level interrupt makes a request to
set priority, the request should be routed via the multilevel interrupt
API. Otherwise, we will configure the interrupt priority for one of the
core interrupts on the ARC controller (which is usually not what the API
caller wants)
This occurs because the ARC interrupt priority register encodes
interrupts from 0-255, so a multilevel interrupt number would simply be
masked to the lowest 8 bits (which matches the interrupt number of that
device's parent controller)
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Signed-off-by: Alex Apostolu <aapostolu@tenstorrent.com>
Update the arch_irq_enable/disable functions to support multilevel
interrupts on the ARC architecture.
Signed-off-by: Aaron Fong <afong@tenstorrent.com>
Signed-off-by: Alex Apostolu <apostolu240@gmail.com>
arch_buffer_validate() on ARC computes the end address of the
validated range using unprotected unsigned addition. When addr+size
wraps around the 32-bit address space the check can succeed for a
buffer that spans non-user-accessible memory, violating the
arch_buffer_validate() contract.
Add overflow detection using u32_add_overflow(), mirroring the fix
already applied to ARM32 (PR #23239) and Xtensa (PR #109000).
Handle size == 0 explicitly so that size - 1 does not underflow.
This affects ARC MPUv2/v3/v4/v6/v8 implementations.
Fixes#113832
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
The loop read s[counter] before checking whether maxsize bytes had
been examined (lp_count was set to maxsize + 1 and tested only after
the load), so it read s[maxsize] when the first maxsize bytes were
all non-NUL and dereferenced s[0] when maxsize == 0, violating the
strnlen() semantics required by arch_user_string_nlen(). The
over-read byte cannot change the returned length, but if it is not
accessible the exception fixup reports a spurious error and callers
reject valid input with EFAULT.
Set lp_count to maxsize and check it before the load instead.
Verified by build and disassembly for qemu_arc/qemu_arc_em; no ARC
simulator is available locally, runtime coverage is expected from
the syscalls suite on nsim platforms in CI.
Fixeszephyrproject-rtos/zephyr#113722
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
arc_vpx_sem_init() initialized vpx_sem[0] once per CPU instead of
initializing each CPU's semaphore: the loop passed the array (decaying
to &vpx_sem[0]) to k_sem_init() rather than the i-th element, leaving
the semaphores of CPUs 1..N-1 uninitialized on multi-core
configurations.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The architecture idle paths call sys_trace_idle() and
sys_trace_idle_exit() to notify subscribers when the CPU enters and
leaves the idle state. These calls were guarded by CONFIG_TRACING,
which tied idle-time accounting to the tracing subsystem even though
no tracing backend is required to service the hooks.
Introduce a hidden Kconfig symbol, SYS_IDLE_HOOKS, that any subsystem
needing these notifications can select, and have TRACING select it.
Switch the idle-path guards in every architecture and SoC that emits
the hooks from CONFIG_TRACING to CONFIG_SYS_IDLE_HOOKS. Because
TRACING selects the new symbol, existing tracing behaviour is
unchanged; the change only lets non-tracing consumers receive the
hooks.
This is a prerequisite for building the CPU load module without the
tracing subsystem.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enables the __nocache attribute on ARCv2 with MPU v6.
Adds REGION_NOCACHE_ATTR and the DC bit to the public
MPU header so boards can declare nocache regions.
_region_init() preserves the DC bit through region programming.
Boards opt in by adding a nocache entry to mpu_regions[],
placed first for higher priority than SRAM.
nsim_hs_mpuv6 is the first consumer.
Adds a smoke test under tests/arch/arc/arc_nocache covering placement,
alignment, and .di-based cache-bypass validation on nsim_hs_mpuv6.
Signed-off-by: Rishav Chakraborty <reshav01@gmail.com>
Adds arch-level instruction memory API with functions
for memcpying / memsetting and determining whether a
region is in instruction memory. Implement API for
Xtensa and ESP32, with support for word granular access.
Adds definitions for instruction memory to
Xtensa ESP32 platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, I/DCACHE_LINE_SIZE are redefined and set to the given
default value even if the dependency D/ICACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
kernel.h implies kernel_structs.h via kernel_includes.h, making
explicit inclusion of kernel_structs.h unnecessary whenever kernel.h
is already included in the same translation unit.
Remove the redundant includes across arch, boards, drivers, kernel,
lib, samples, subsys, and tests trees.
in include/zephyr/kernel_structs.h:
* 2. kernel.h shall imply kernel_structs.h, such that it shall not be
* necessary to include kernel_structs.h explicitly when kernel.h is
* included.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add interrupt locking to arc_core_mpu_buffer_validate() to be atomic.
The function iterates through MPU regions using bank selection, which
requires multiple register accesses. Without interrupt protection, an
interrupt or context switch during iteration can corrupt the bank
selection state, causing incorrect region lookups and spurious access
denials.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
Upgrades the thread user_options to 16 bits from an 8-bit value to
provide more space for future values.
Also, as the size of this field has changed, the values for the
existing architecture specific thread options have also shifted
from the upper end of the old 8-bit field, to the upper end of
the new 16-bit field.
Fixes#101034
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
soc_per_core_init_hook() is usually called from arch_kernel_init() and
arch_secondary_cpu_init() which are C functions. As such, there is no need
to check for CONFIG_SOC_PER_CORE_INIT_HOOK since platform/hooks.h provides
a no-op function-like macro implementation if the Kconfig option is not
enabled.
Remove the Kconfig option check from all files.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
soc_prep_hook() is always called from z_prep_c() which is implemented
as a C function. As such, there is no need to check for the associated
CONFIG_SOC_PREP_HOOK since the platform/hooks.h header will define hooks
as no-op function-like macros if their associated Kconfig isn't enabled.
Remove the Kconfig check from all arch implementations of z_prep_c() and
call soc_prep_hook() directly instead, to avoid duplicating the Kconfig
check already performed in platform/hooks.h
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
z_prep_c does not return, mark it as such consistently across
architectures. We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.
All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.
The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Not really a kernel feature, more for architecture, which is reflected
in how XIP is enabled and tested. Move it to architecture code to keep
which much of the 'implementation' and usage is.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The intent of arch_coprocessors_disable() is to replace
arch_float_disable() in halt_thread() for the FPU will not
always be the only coprocessor that will need to be disabled.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
ARC was using this method already in a custom way and was different from
all other architectures, lets make this generic.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Just include <zephyr/arch/exception.h> in architecture code. The file
redirects to the correct implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for CONFIG_ROM_START_OFFSET on ARC processors. Note that the
arc ISA requires vector table offset to be at a 1024 KiB boundary, so
the default ROM_START_OFFSET when using MCUBoot must be increased.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Added configurable support for L1 cache region operations,
which offers improved performance over line operations.
Added configurable support for SLC (system level cache).
Added support for entire cache operations: flush_all,
invd_all, flush_and_invd_all.
Reviewed-by: Aaron Komisar <aaron.komisar@tandemg.com>
Signed-off-by: Yanir Levin <ylevin@gsitechnology.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `arch`, `boards`, `kernel`, `modules`,
`samples`, and `share` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
As per Zephyr guidelines regarding the use of inclusive language, apply
the following replacements:
- s/master/primary/g
- s/slave/secondary/g
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
__cxa_atexit was originally defined by the IA64 C++ ABI, but it has been
adopted by other C++ implementations since then. This function is already
present in lib/cpp/api/cpp_dtors.c, which is built by default when C++
support is enabled, so we don't need another copy in the MWDT-specific
code.
Signed-off-by: Keith Packard <keithp@keithp.com>
The RISC-V port of llext requires additional parameters for
handling non-adjacent HI20/LO12 relocations in arch_elf_relocate():
the current extension (struct llext), the current extension loader
(struct llext_loader), the current section header (elf_shdr_t) and
the current symbol (elf_sym_t).
This changes the signature of arch_elf_relocate accordingly.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The exception fault handler function is named _Fault which is inconsistent
with all other arch-specific functions present in Zephyr. This patch
replaces the name with z_arc_fault.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
Mostly a revert of commit b1def7145f ("arch: deprecate `_current`").
This commit was part of PR #80716 whose initial purpose was about providing
an architecture specific optimization for _current. The actual deprecation
was sneaked in later on without proper discussion.
The Zephyr core always used _current before and that was fine. It is quite
prevalent as well and the alternative is proving rather verbose.
Furthermore, as a concept, the "current thread" is not something that is
necessarily architecture specific. Therefore the primary abstraction
should not carry the arch_ prefix.
Hence this revert.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
`_current` is now functionally equals to `arch_curr_thread()`, remove
its usage in-tree and deprecate it instead of removing it outright,
as it has been with us since forever.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
