The board target for emulation of nRF52811 on nRF52840 DK, so far
known as nrf52811_pca10056, is renamed to nrf52840dk_nrf52811.
Its documentation and all references to its name in the tree are
updated accordingly. Overlay and configuration files specific to
this board are also renamed, to match the new board name.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The nRF52840 DK board target, so far known as nrf52840_pca10056,
is renamed to nrf52840dk_nrf52840.
Its documentation and all references to its name in the tree are
updated accordingly. Overlay and configuration files specific to
this board are also renamed, to match the new board name.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This board is no longer a Preview DK but it is still described as such
in its documentation. Update its description and picture.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Added device tree nodes and associated headers for
defined uarts on the stm32g0 and stm32g07x 8x parts.
Tested with uart on stm32g071rb disco board with usart3 going to stlink.
Using shell.
Signed-off-by: Kieran Levin <ktl@frame.work>
Convert older DT_INST_ macro use in microchip drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in atmel sam drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert older DT_INST_ macro use in sifive drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There is a new init level SMP that was just added, and this module needs
to take it into account.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert older DT_INST_ macro use in STM32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Updated howto "create struct devices in a driver" section to use
DT_INST_FOREACH instead of manual per-instance macros.
Signed-off-by: Ioannis Papamanoglou <iopapamanoglou@gmail.com>
With this macro device drivers can call macros and functions
on every device instance compatible to that driver.
This makes it possible to make drivers agnostic to the
potential counts of instances.
Sidenote: Introduces helper macro DT_CALL_WITH_ARG.
Signed-off-by: Ioannis Papamanoglou <iopapamanoglou@gmail.com>
The primary problem was that the callback was being invoked twice,
which broke the tests.
A secondary issue is that when two level tests occur consecutively the
second will fail. Instrumentation confirms that the registers are
being configured correctly, and ip indicates that the condition was
detected, but the interrupt does not occur. Tests pass as long as no
level test precedes the failing test.
It's not clear whether this is an issue with the PLIC, or the GPIO
implementation (hardware or software). As "normal" GPIO applications
appear to work we'll run with it and keep an issue open.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Use zero-padded 32-bit hex constants for the start address and
length so the fields are easier to compare. Correct the span of
the priority/claim region.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The Atmel DFP headers define two "component typedef styles": RFO and
NTO; where the latter makes use of bit field structs to access hardware
registers.
The default component typedef style assumed by the DFP headers (i.e.
when `COMPONENT_TYPEDEF_STYLE` is not explicitly defined) is "RFO" and
this is indeed the component typedef style used throughout the Zephyr
Atmel SAM drivers, except in the particular instance which this commit
addresses.
The use of `GMAC_TA_Type` bit field struct, which is an "NTO" style
construct, is no longer possible with the latest DFPs because
conditional compilation checks for the bit field struct definitions
were added to restrict the use of such constructs to only when the
global component typedef style is set to "NTO".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The new Atmel DFP USBHS component headers provide mode-specific
interrupt register field definitions that replace the generic
definitions (e.g. `USBHS_DEVEPTISR_RXSTPI` for a control endpoint is
now `USBHS_DEVEPTISR_CTRL_RXSTPI`).
This commit updates the Zephyr SAM USBHS driver to use the new
mode-specific interrupt register field definitions.
In addition, it maps the generic definitions to the mode-specific
definitions, as the revision A variant headers (e.g. same70a) in the
latest DFPs, at the time of writing, still provide only the generic
definitions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the hal_atmel entry in the west.yml to pull in the
SAME70 DFP version 2.4.166.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Convert older DT_INST_ macro use in esp32 drivers to the new
include/devicetree.h DT_INST macro APIs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename DT_INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 defines to something
non-DT prefixed. This way we know which defines are one's we generate
and which ones are driver created. It should be easy enough to replace
these INST_{0,1,2}_ESPRESSIF_ESP32_UART_IRQ_0 define with DTS generated
one macros once esp32 has interrupt controller support in DTS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix so that different isochronous synchronization modes can be used.
It filters out the synchronization mode before sending the endpoint
type to drivers.
Signed-off-by: Johan Carlsson <johan.carlsson@teenage.engineering>
LOG_LEVEL_SET was ignoring level argument and was setting default
log level always.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Update the ticks_current value on last stopped ticker
instance, so that when a new ticker instance is started
the anchor ticks calculation uses the correct current tick
with respect to supplied anchor ticks.
Fixes#23805.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
AN521 is a dual core FPGA on MPS2+ with both cores are CM33. Add openAMP
to support on it.
Core 0 is primary core, it runs as master, core 1 is remote, it runs
as slave.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
