XCC does not support compiler option -fno-defer-pop.
Change-Id: Ic47714331502b10e5e1e510984991615fe801696
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Provide generic support for running zephyr kernels on xtensa QEMU and
map D_233L SoC to dc233c QEMU core.
Change-Id: Ie804588f750213a7cc54dbc95c86ee4d62ba1ea5
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This platform is not a real board but let user handle the xtensa
simulator just like a board.
This is needed until a qemu like simulaotr is added to Xtensa.
Change-Id: I54ab28e86eea956cf85af3ee9b4a10f0d531e54d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.
Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
When test GPIO_INT_EDGE, there is no code to skip GPIO_INT_LEVEL
and jump to the end of the function. So GPIO_INT_LEVEL will
always be checked (Besides, it't always true), even if it's
testing GPIO_INT_EDGE, which will cause GPIO_INT_EDGE cases fail.
Add a goto statement for GPIO_INT_EDGE to skip GPIO_INT_LEVEL.
Jira: ZEP-1685
Change-Id: I10ce21c04c49f34aafdc2cd2f60f3e5377d6f1f5
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
This test case uses PWM0 port to test PWM on Quark Se.
However PWM0 port on Quark D2000 is initialized as tdo,
not PWM0 and disabling tdo will kill JTAG on D2000. So
use PWM1 and add PINMUX setting code to configure PIN_24
as PWM1 port, then the case will work on D2000 board.
Change-Id: Ib28d4750dac7396529388b781fb64bde048139d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
the commit test below adc driver api with different resolutions
and modes
adc_enable()
adc_read()
adc_disable()
move original adc test to adc_simple folder
Change-Id: I016b5e67a5d89fc8d5ae76f33799e5d3eb3e1cf8
Signed-off-by: jing wang <jing.j.wang@intel.com>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Idd2360847a467af6afdd9fbed8f87a620d9ed2f7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The current I2C API provides inline functions to access 1 byte
register addresses. This commit adds a set of I2C inline functions
as shortcuts to handle:
- 16 bit register addressing. A family of functions that allows to
handle 2 byte register addressing and can receive the address
parameter as a simple variable. This allows a developer to handle
the address as a C constant or macro.
- Multiple byte addressing. A family of functions to access
registers with a configurable register address size. This family
of functions handle register addressing of any size but receives
the address parameter as a byte array.
Change-Id: Id369ab9eaad7eea807554371d3a520f67dc2e0f2
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
Update the dma loop transfer sample app to use the new
dma api interfaces. This change is based on the api change
and the updated dma driver.
A RFC was posted recently on this.
Jira: ZEP-873
Change-Id: I289e2e08d4c775a833bf3d585d2706a903edd0bc
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.
The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.
Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.
Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Binding of the device failed due to incorrect device name. Update
to use the correct device name.
Jira: ZEP-1704
Change-Id: I6ca23a439357592c9c974ca746bccc35e77d996d
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
This test is intended to verify that the SW ISR and vector tables
have been populated correctly.
Change-Id: Ic7f50c02dc0807d7ddefa710da67f818ff707ad6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a new mechanism for generating interrupt tables which will
be useful on many architectures. It replaces the old linker-based
mechanism for creating these tables and has a couple advantages:
1) It is now possible to use enums as the IRQ line argument to
IRQ_CONNECT(), which should ease CMSIS integration.
2) The vector table itself is now generated, which lets us place
interrupts directly into the vector table without having to
hard-code them. This is a feature we have long enjoyed on x86
and will enable 'direct' interrupts.
3) More code is common, requiring less arch-specific code to
support.
This patch introduces the common code for this mechanism. Follow-up
patches will enable it on various arches.
Issue: ZEP-1038, ZEP-1165
Change-Id: I9acd6e0de8b438fa9293f2e00563628f7510168a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order to set breakpoints after waking up from sleep,
it is needed to save DR0/DR1/DR2/DR3 and DR6/DR7.
As DR4/DR5 are reserved or mapped to DR6/DR7, they are not saved.
Patch2 : Added compile time checks for debug build or soc_watch
build for Intel Energy analysis.
Patch3 : Avoid clobbering of edx.
JIRA: ZEP-1681
Change-Id: I62fbedca16953d57196420ecae4fb93c785bb4a5
Signed-off-by: Sarath R Nair <sarath.nandu.ramachandran.nair@intel.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: Ic625749309773611c0c6ba2905e9420e98947dae
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I10d04c2949ad2a390d4c1159d2342c73108a58b7
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This patch adds in the include to get the CONFIG_SRAM definitions on
systems which are using device tree generation.
Change-Id: Ie61efbcdfc900a2c682a2fb8bbaecb61071a20f8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file. This was done to simplify the
includes required for files. Only two files will include the dts
generated include file directly: arch.h and the linker.ld
Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.
Jira: ZEP-1568
Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
_SCS_CPACR_CP10_Pos and _SCS_CPACR_CP11_Pos come from scs.h, we have
versions defined in cmsis.h we should be using instead.
Change-Id: Icd8db02000bbc9ef8b2cf89d359e008f62a7d5e9
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverted:
_ScbMemFaultMmfarReset
_ScbBusFaultBfarReset
_ScbUsageFaultAllFaultsReset
To use direct CMSIS register access.
Also removed scb.h and references as there is no longer any code in it.
Jira: ZEP-1568
Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.
Jira: ZEP-1568
Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converted access to CFSR MMFSR, BFSR, and UFSR to use direct CMSIS
register access when printing out the values of those registers.
Jira: ZEP-1568
Change-Id: I7969bb81346327637140ec23d91422a6bfaef032
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Coverted:
_ScbBusFaultAddrGet
_ScbMemFaultAddrGet
To use direct CMSIS register access
Jira: ZEP-1568
Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
