In the 32-bit bitfield pinctrl, the bits from b31 to b24 are representing
the PIN function. The correct mask value then must be 0xFFu.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This commit should address the #73803 issue
where the DMA node does not provide support
for the #dma-cells binding. Peripherals should
specify one or more DMA channels via the dmas
and optionally dma-names DT properties.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add ENET_1G clock value to the RT11XX CCM version.
Implemented enabling ENET_1G clock and getting its frequency.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Introduce the stm32h7RS serie to the pin control driver,
New GPIO port M, N, O, P
Then add the complete list and from A to P (16 port
coded on 5 bits)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce the stm32h7RS serie to the clock_controller,
based on the stm32h7 clock driver
Datasheet DS14359 rev 1 gives CPU max freq of 500MHz
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the support of the STM32H7RSX to the
include/zephyr/dt-bindings/reset/stm32h7_reset.h
which differs from the stm32h7 with an APB5 bus
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce a custom STM32_GPIO_WKUP GPIO flag.
Use the newly introduced stm32_pwr_wkup_pin_cfg_gpio() public
function to configure GPIO pins, that have the STM32_GPIO_WKUP
flag in DT, as sources for STM32 PWR wake-up pins, on the condition
that there is a wake-up pin that corresponds to each of them.
These GPIO pins can then be used to power on the system after Poweroff
like a reset pin.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add DT binding for stm32 PWR peripheral that controlls wake-up pins.
This binding primarily introduces wake-up pins configuration in
a unifed way that takes into consideration the variations between
STM32 SoC series & facilitates the association of GPIO pins with
their corresponding wake-up pins.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
when GPIO_INT_WAKEUP flag is used in a DT gpios property
the gpio_dt_flags_t var that holds the flags overflows
Hence moving GPIO_INT_WAKEUP flag from bit 28 to bit 6
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add flag STM32_DMA_16BITS as a combination of
STM32_DMA_PERIPH_16BITS and STM32_DMA_MEM_16BITS
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
New nRF54H20 SoC series expose more ports, e.g. P9, so reserve more bits
for the Port+Pin field.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add binding representing the peripheral reset controller
of the NXP LPC SYSCON heritage hardware including SYSCON
itself and the newer RSTCTL.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Previous value just activated the ability to trigger for both edges,
without (de)-activating the gpio. This caused an assrtion error in GPIO.h.
Fixes#71227
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
The new bindings for the stm32 xspi is for new stm32 devices with
XSPI peripherals like the stm32h5 serie. This is close to the octo-spi.
Adapt the flash controller constants to the XSPI model especially.
This is done through a new xspi.h definition file.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Move the Domain IDs from `nrf54h20.dtsi` into its own header file.
Additionally, include another header with Owner IDs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add binding for adi SDP-120 connector and header file
with marcos to map signals using signal names.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Added EXMIP pinctrl definitions, which allow selecting pin functions by
name in DTS. The definitions are added, but not used in pinctrl_nrf.c.
The nrf-regtool reads the pinctrl configuration and applies the settings
using different mechanisms.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Add support for the MSI clock on the STM32WL family. This is needed for
instance to set the RNG clock domain to MSI in the device tree when not
using the PLL.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This update integrates I2C support with the pinctrl_configure_pins api
within the pinctrl_gecko driver.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
1. The only valid values of MCLKD clock frequency
are between 40Mhz to 50Mhz.
2. If DMA is used, the APB4_CLK clock frequency must
be equal to or higher than 20Mhz.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
The lpadc driver needs to obtain its functional clock to configure
the acquisition time. This patch add support for I.MX RT three digit
parts, I.MX RT11xx parts, and LPC parts.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Michael Hope
