Add bindings for NXP MIPI CSI-2 Rx which is a MIPI CSI-2 receiver
connecting a camera sensor to the NXP CSI.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver with
TI Single-Wire interface (EasySet) protocol.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
Convert the ST7735R display to use the MIPI DBI API. Boards and overlays
using this display are also updated.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The RTXXX and RW61X DT are using syscon compatible
depsite not having a syscon. This is a technical debt
to remain aware of. The reason they use these compatibles
is to use the syscon driver which is a shim to an SDK API
that is somewhat similar to syscon.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Include reset device binding in some of the NXP LPC
IP bindings to be able to add the resets property.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding representing the peripheral reset controller
of the NXP LPC SYSCON heritage hardware including SYSCON
itself and the newer RSTCTL.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Clarify that there needs to be a cell named "id" in order
to be usable by the reset controller macros.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Fix mcxn94x flash write-block-size from 16 to 128.
- Fix flash_program() return error 0x65,
that means "Address or length does not meet the required alignment."
- The mcxn94x Flash ROM API flash_program() start address and
the length must be 128 bytes-aligned.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
port infineon CAT1A (psoc6) to HWMv2:
1. move dts\arm\cypress\** to dts\arm\infineon\cat1a\legacy
2. remove dts\arm\cypress\**
3. rename dts\arm\infineon\psoc6 to dts\arm\infineon\cat1a
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Previous value just activated the ability to trigger for both edges,
without (de)-activating the gpio. This caused an assrtion error in GPIO.h.
Fixes#71227
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
Remove the "snps,designware-spi" compatible from the EXMIF node in
nRF54H20i, as the spi_dw driver cannot be used for this peripheral
without Nordic-specific modifications that are not present upstream.
An attempt to do so (just setting CONFIG_SPI=y will cause that,
as the driver initialization function will be executed then) results
in a bus fault.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add driver for TSic 206/306/316/506F/516/716 temperature sensor.
The driver uses PWM capture driver to read a single wire with
Manchester-like encoding.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Move it to a common file named `zephyr,memory-common.yaml`, which
replaces `zephyr,memory-attr.yaml` and takes its contents as well.
This is so that another binding, e.g., `vnd,memory-region`, can support
being combined with the `zephyr,memory-region` binding like so:
node@deadbeef {
compatible = "vnd,memory-region", "zephyr,memory-region";
zephyr,memory-region = "NAME";
...
};
To allow this, edtlib would require `vnd,memory-region` to include the
property definitions from this new common file.
The same can't be done by including `zephyr,memory-region.yaml` directly
because that file marks the property in question as always required, and
it shouldn't be required whenever the `vnd,memory-region` compatible is
used on its own.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add the Kconfig options and use the aliased
addresses for the bootcode regions of the IMX7D
and IMX6SX SOCs to allow the Linux rproc
framework to load the irq-vectors into
the correct memory areas.
Activating this option might enlarge the bin
file if the zephyr,flash and rom_start chosen
region addresses are not matching.
It is up to the user to enable this feature
based on code location choices (OCRAM, DDR, TCM...).
Signed-off-by: Jérémy LOCHE - MAKEEN Energy <jlh@makeenenergy.com>
By default, the QSPI region is marked as EXTMEM and inaccessible
(see #57467), mark the first 64MB as IO on stm32f769i_disco.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The gpio-emul driver does not actually require any reg property,
since it is not in the physical memory map of any device. So
let's remove that property from the bindings.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Remove all CAN controller "bus-speed" and "bus-speed-data"
properties. These all use the default bitrates set via Kconfig.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Set the default initial bitrates globally via Kconfig. The initial bitrates
can still be overridden using the "bus-speed" and "bus-speed-data"
devicetree properties.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove nxp_ground_select property.
Delete the use of NXP vref peripheral CSR register REFL_GRL_SEL bit.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
PHYTEC has multiple offices in different locations like
the US, France, India and China. The headquarter is located in
Germany. Since now 50% of the PHYTEC boards are from the US
office, we should drop 'Messtechnik GmbH', which is the offical
title of the German office, and keep the name more general.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Define the xspi node instead of ospi. Note that RCC CCIPR4 register
keeps the OCTOSP1 for clock domain selection.
Change the header file to xspi for the stm32 devices with xspi
peripheral. Keep the flash_controller/ospi.h for bindings compatibilty.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The new bindings for the stm32 xspi is for new stm32 devices with
XSPI peripherals like the stm32h5 serie. This is close to the octo-spi.
Adapt the flash controller constants to the XSPI model especially.
This is done through a new xspi.h definition file.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add driver, together with the corresponding dts binding and node in
the nRF54H20 SoC definiton, for the nRF temperature sensor that cannot
be accessed directly but only through nRF Services (nrfs) layer.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit makes the devicetrees of the targets that are based on the QEMU
`virt` machine more consistent with the rest of the RISC-V targets in
Zephyr by:
* adding the `riscv,isa` property
* adding a compatible string which uniquely identifies the `virt` core
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add USDHC0 node to the mcxn94x devicetree. This node describes the one
instance of the Ultra Secured Digital Host Controller IP present on the
MCXN94x series SOCs.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CSI can connect to either a camera sensor (as on i.MX RT10xx) or
a MIPI CSI-2 receiver (as on i.MX RT11xx). To be generic, change the
naming from sensor to source.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Add initial HID device support. Unlike the existing HID implementation,
the new implementation uses a devicetree to instantiate a HID device.
To the user, the HID device appears as a normal Zephyr RTOS device.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add DT node entries to RW for DAC and ADC.
Support the SOC required initialization of the DAC and ADC on RW.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commits adds required pinctrl node to provide the corresponding SIO
clock selection for the Serial Port under the different VOSCCLK.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The clk, dqs and ncs pins can be remapped between OSPI instances, but the
driver doesn't support it, yet. Therefore replace hard coded numbers to
device tree optional properties.
Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
iMXRT1042 SOC should be clocked at 528 MHz maximum. Correct the clock
setup to use the system PLL.
Fixes#70755
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of the system pll on the iMXRT10xx series parts, via
a fractional pll node under the CCM module.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adding required flag to the current-speed as without this driver
does not compile.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This commit adds an ieee802154 node to the list of nRF54H20 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio indirectly through cpurad.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Gives number of the Extended Interrupts and Event Controller (EXTI)
interrupt line connected to the RTC Alarm event.
Used on all series, except WBAX & U5X, where RTC Alarm interrupt is
routed directly to Nested Vectored Interrupt Controller (NVIC) and to
Power Control (PWR) wake-up pins.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Move the Domain IDs from `nrf54h20.dtsi` into its own header file.
Additionally, include another header with Owner IDs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This change allows to use DTR line driven from external serial port
that when active (low) will prevent UART device from going to sleep.
It will also wake up platform when DTR line becomes active.
DTR line is often activated in serial port connected to host computer
when operating system opens serial device like COMx for Windows
or /dev/ttyACMx /dev/ttyUSBx for Linux based systems.
DTR line (specified in device tree) will be used by WAKEUP and PDC
controllers (via GPIO driver) to handle DTR line changes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
This change allows to wake up UART from sleep mode when
low level on inactive UART is detected during platform sleep.
Timeout can be specified for each UART separately in device tree.
If one of the UARTs is selected as console sleep timeout is taken
from Kconfig same way other platform configure same functionality
using CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
UART2 and UART3 (unlink UART) do support hardware flow control.
This simply add necessary flag that is already handled in the code.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Correction of the reg address of enet2 for nxp_rt1060.
Regression introduced at 537d5c310c
Signed-off-by: Matthias Alleman <matthias.alleman@basalte.be>
This commit adds flash controller instance for Ambiq Apollo3 Blue SOC
and Apollo3 Blue Plus SOC.
Also create the partitions on this flash controller node for apollo3_evb
and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The emulated GNSS driver behaves like a GNSS, implementing
device pm and the GNSS APIs, using only kernel features (
zephyr work queue and uptime) making it buildable on all
zephyr targets.
The purpose of this device driver is to tailor and validate
the gnss api test suite.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add mfd_adp5585 and gpio_adp5585 driver. This driver enables ADP5585
as an GPIO expander.
This chip is used as an GPIO expander on i.MX93 EVK. GPIO pinctrl,
read/write and interrupt is supported.
Note that ADP5585 has 2 GPIO banks with 5 pins each. The driver combines
two group into a 16-bit port. Index 0~4 correspond to R0~R4 lines, index
8~12 correspond to C0~C4 lines. Index 5~7 is reserved unavailable.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The counter driver needs to know what is the maximum
counting frequency of each timer peripheral.
Let's add it to its DT.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add binding for adi SDP-120 connector and header file
with marcos to map signals using signal names.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added EXMIF peripheral DTS description and bindings.
The peripheral operates as an SPI device.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
In the <board>.dts file, the definition for usart0 was found to be
redundant as the same information is already provided in the included
.dtsi file. this commit removes the duplicate definition of usart0,
resulting in a cleaner and more maintainable device tree configuration.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Add mdio node for h5 and h7 series.
Since MDIO registers are part of the same ETH hw IP, keeping mdio
node just as a child of mac/eth, cannot see as appropriate to assign
an adddress to it.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
MDIO is part of the ETH IP, but some phy chip may need a
specific phy driver to set up certain vendor registers enabling
particular features.
Add support for stm32 mdio access.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Add Sequans GM02S modem binding using the sqn vendor prefix.
The modem has an active low reset signal.
Signed-off-by: Thibo Verheyde <thibo@dptechnics.com>
Intial driver adding intial script to receive only GGA, RMC and GSV
NMEA messages, configuring fix rate, setting enabled system and adding
power management with the module on-off pin.
Signed-off-by: Jeronimo Agullo <jeronimoagullo97@gmail.com>
Set RNG address to its non-secure alias.
See RM0493 STM32WBA5 Reference manual for details.
Using the secure alias (0x5..)instead of the non-secure alias (0x4..)
for this peripheral results in a SecureFault during kernel init if
TrustZone is activated, Zephyr is running as NSPE and RNG is
enabled.
Signed-off-by: Louis Feller <louis.feller@st.com>
Commit 246ea739bb ("dts/arm/st: wl: increase Sub-GHz SPI frequency to
12MHz") increased the Sub-GHz to 12 MHz. This matches the SX126x
datasheet, but there is no information about the maximum speed in the
STM32WL datasheet or reference.
This works fine when not using DMA. However with DMA activated (adding
entries to the device-tree and enabling CONFIG_SPI_STM32_DMA), I have
encountered some rare corruption. When it happens, the read from the
Sub-GHz device gets an extra 0x00 byte prepended, which confuses the
LoRaMac-node library and causes reception failures. Decreasing the
frequency to the next round number, that is 8 MHz (i.e. increasing the
prescaler from 4 to 6) fixes all the issues I encountered.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Spell checking tools do not recognize "iff", replace with "if and only if".
See https://en.wikipedia.org/wiki/If_and_only_if
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
