In order to de-duplicate 2 macros with the same use,
merge BUILD_ASSERT(), BUILD_ASSERT_MSG() into one macro.
Make BUILD_ASSERT_MSG() deprecated.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This reverts commit 974aa3add4.
Pull Request #23437 was merged by mistake with an invalid manifest.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
In order to de-duplicate 2 macros with the same use,
merge BUILD_ASSERT(), BUILD_ASSERT_MSG() into one macro.
Make BUILD_ASSERT_MSG() deprecated.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This commit introduces the `COMPILER_ISA_THUMB2` symbol to allow
choosing either the ARM or Thumb instruction set for C code
compilation.
In addition, this commit introduces the `ASSEMBLER_ISA_THUMB2` helper
symbol to specify the default target instruction set for the assembler.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Use the special x86 operand modifier 'p' to print the raw value.
This fixes an issue on x86-64 where errors were generated
if a constant larger than INT_MAX was used.
Values larger than UINT_MAX are still unsupported (on any arch).
Fixes: #22542
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Works like __DEPRECATED_MACRO with a custom message. Can do this for
example:
#define FOO __WARN("Please use BAR instead") ...
Implement __DEPRECATED_MACRO with __WARN().
Useful for https://github.com/zephyrproject-rtos/zephyr/pull/21506.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
To be able to successfully compile the kernel for the ARM64 architecture
we have to tweak the compiler-related files to be able to use the
AArch64 GCC compiler.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The __deprecated symbol can be pre-defined to avoid warnings of use of
deprecated API in tests of that API. Enable that same feature for
macros that are deprecated.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit refactors kernel and arch headers to establish a boundary
between private and public interface headers.
The refactoring strategy used in this commit is detailed in the issue
This commit introduces the following major changes:
1. Establish a clear boundary between private and public headers by
removing "kernel/include" and "arch/*/include" from the global
include paths. Ideally, only kernel/ and arch/*/ source files should
reference the headers in these directories. If these headers must be
used by a component, these include paths shall be manually added to
the CMakeLists.txt file of the component. This is intended to
discourage applications from including private kernel and arch
headers either knowingly and unknowingly.
- kernel/include/ (PRIVATE)
This directory contains the private headers that provide private
kernel definitions which should not be visible outside the kernel
and arch source code. All public kernel definitions must be added
to an appropriate header located under include/.
- arch/*/include/ (PRIVATE)
This directory contains the private headers that provide private
architecture-specific definitions which should not be visible
outside the arch and kernel source code. All public architecture-
specific definitions must be added to an appropriate header located
under include/arch/*/.
- include/ AND include/sys/ (PUBLIC)
This directory contains the public headers that provide public
kernel definitions which can be referenced by both kernel and
application code.
- include/arch/*/ (PUBLIC)
This directory contains the public headers that provide public
architecture-specific definitions which can be referenced by both
kernel and application code.
2. Split arch_interface.h into "kernel-to-arch interface" and "public
arch interface" divisions.
- kernel/include/kernel_arch_interface.h
* provides private "kernel-to-arch interface" definition.
* includes arch/*/include/kernel_arch_func.h to ensure that the
interface function implementations are always available.
* includes sys/arch_interface.h so that public arch interface
definitions are automatically included when including this file.
- arch/*/include/kernel_arch_func.h
* provides architecture-specific "kernel-to-arch interface"
implementation.
* only the functions that will be used in kernel and arch source
files are defined here.
- include/sys/arch_interface.h
* provides "public arch interface" definition.
* includes include/arch/arch_inlines.h to ensure that the
architecture-specific public inline interface function
implementations are always available.
- include/arch/arch_inlines.h
* includes architecture-specific arch_inlines.h in
include/arch/*/arch_inline.h.
- include/arch/*/arch_inline.h
* provides architecture-specific "public arch interface" inline
function implementation.
* supersedes include/sys/arch_inline.h.
3. Refactor kernel and the existing architecture implementations.
- Remove circular dependency of kernel and arch headers. The
following general rules should be observed:
* Never include any private headers from public headers
* Never include kernel_internal.h in kernel_arch_data.h
* Always include kernel_arch_data.h from kernel_arch_func.h
* Never include kernel.h from kernel_struct.h either directly or
indirectly. Only add the kernel structures that must be referenced
from public arch headers in this file.
- Relocate syscall_handler.h to include/ so it can be used in the
public code. This is necessary because many user-mode public codes
reference the functions defined in this header.
- Relocate kernel_arch_thread.h to include/arch/*/thread.h. This is
necessary to provide architecture-specific thread definition for
'struct k_thread' in kernel.h.
- Remove any private header dependencies from public headers using
the following methods:
* If dependency is not required, simply omit
* If dependency is required,
- Relocate a portion of the required dependencies from the
private header to an appropriate public header OR
- Relocate the required private header to make it public.
This commit supersedes #20047, addresses #19666, and fixes#3056.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
There are two set of code supporting x86_64: x86_64 using x32 ABI,
and x86 long mode, and this consolidates both into one x86_64
architecture and SoC supporting truly 64-bit mode.
() Removes the x86_64:x32 architecture and SoC, and replaces
them with the existing x86 long mode arch and SoC.
() Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64.
() Updates samples and tests to remove reference to
qemu_x86_long.
() Renames CONFIG_X86_LONGMODE to CONFIG_X86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This header makes a call to posix_print_error_and_exit,
but pulls in no prototype.
Linker scripts use nothing in this file, move the #ifndef
_LINKER to the toplevel.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
MAX() and MIN() were evaluating arguments twice. If arguments are
functions they were called twice which resulted in bigger code
and potential misbehavior.
Added alternative macros (Z_MAX, Z_MIN) which can be used instead.
Macros have usage limitations thus they are not replacements. They
are also relying on GCC extension thus placed in gcc.h
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
__BYTE_ORDER__ preprocessor definition is not defined by older versions
of GCC. The definitions for __ORDER_BIG_ENDIAN__,
__ORDER_LITTLE_ENDIAN__ and __BYTE_ORDER__ by automatic detection using
arch-specific endianness definitions have been added.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Compilers based on Clang provide a __has_builtin(x) macro which can be
used to detect in the preprocessor if a given builtin function is
supported by the compiler.
For other compilers (notably GCC), we provide an alternative definition
of HAS_BUILTIN(x) that depends on the toolchain-specific header file to
declare which builtin functions are supported based on the current
compiler version.
Signed-off-by: Jakob Olesen <jolesen@fb.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Instead of having to enable ramfunc support manually, just make it
transparently available to users, keeping the MPU region disabled if not
used to not waste a MPU region. This however wastes 24 bytes of code
area when the MPU is disabled and 48 bytes when it is enabled, and
probably a dozen of CPU cycles during boot. I believe it is something
acceptable.
Note that when XIP is used, code is already in RAM, so the __ramfunc
keyword does nothing, but does not generate an error.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Using __ramfunc to places a function in RAM instead of Flash.
Code that for example reprograms flash at runtime can't execute
from flash, in that case must placing code into RAM.
This commit create a new section named '.ramfunc' in link scripts,
all functions has __ramfunc keyword saved in thats sections and
will load from flash to sram after the system booted.
Fixes: #10253
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This was never a long-term solution, more of a gross hack
to get test cases working until we could figure out a good
end-to-end solution for memory domains that generated
appropriate linker sections. Now that we have this with
the app shared memory feature, and have converted all tests
to remove it, delete this feature.
To date all userspace APIs have been tagged as 'experimental'
which sidesteps deprecation policies.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The macros likely() and unlikely() used by the compiler for
optimization are always used inside an if condition.
According to MISRA we need to have bool type and not long.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
compiler_barrier() is itself defined down in this file. Without
adding it, newer versions of GCC (7+) for ARM Cortex-M may mistakenly
coalesce multiple strb/strh/str (store byte/half-word/word)
instructions, which support unaligned access on some
sub-architectures (Cortex-M3 and higher, but not on Cortex-M0),
into strd (store double), which doesn't support unaligned access.
Fixes: #6307
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The logic for using _Static_assert() was a little broken. We were
using it when on GCC 4.6+ AND when __STDC_VERSION__ said we were on
C99 or better. But it's not a C99 feature, it's a C11 feature. And
if GCC provides it as an extension, that's unrelated to a particular
language version. This should have been "GCC 4.6+ OR C11+".
This actually broke on the ESP-32 IDF toolchain, where (when using
-std=c99) the compiler was actually defining a C99 macro instead of
the C11 one, and choosing to use the wrong (and independently broken)
handling incorrectly. Fixes#8093.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch lets a C++ application use more of Zephyr by adding guards
and changeing some constructs to the C++11 equivalent.
Changes include:
- Adding guards
- Switching to static_assert
- Switching to a template for ARRAY_SIZE as g++ doesn't have the
builtin.
- Re-ordering designated initialisers to match the struct field order
as G++ only supports simple designated initialisers.
Signed-off-by: Michael Hope <mlhx@google.com>
Added guards to the toolchain/gcc.h and toolchain/common.h
Those files should never be included directly, but a guard is useful
regardless.
Fixes#5130
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A new arch (posix) which relies on pthreads to emulate the context
switching
A new soc for it (inf_clock) which emulates a CPU running at an
infinely high clock (so when the CPU is awaken it runs till completion
in 0 time)
A new board, which provides a trivial system tick timer and
irq generation.
Origin: Original
Fixes#1891
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
To define a system call, it's now sufficient to simply tag the inline
prototype with "__syscall" or "__syscall_inline" and include a special
generated header at the end of the header file.
The system call dispatch table and enumeration of system call IDs is now
automatically generated.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
_FILE_PATH_HASH appears to be a legacy Diab-ism that doesn't
expand to anything in GCC.
As a result, when linking the combined binary, it's quite
possible that objects in separate C files would be merged
instead of truly being in their own section. This can confound
--gc-sections and result in unused objects still being in
the final binary if one of the other objects with the same
generated section name was actually used.
We instead just use __FILE__. This results in sometimes absurdly-
long section names in the intermediate .o files, but there is no
actual limit to how long section names in ELF binaries can be;
they are not stored directly in headers but instead referenced
as an offset in the .shstrtab section, which has all the section
names stored in it.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add a macro which signals to the compiler that use of the macro is
deprecated.
Example:
#define FOO __DEPRECATED_MACRO bar
Defines FOO to 'bar' but emits a warning if used in code.
Cannot filter out with -Wno-deprecated, so be careful with -Werror.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Provide a BUILD_ASSERT and BUILD_ASSERT_MSG that are based on
_Static_assert when that's available, as its output is easier to read.
Change-Id: Ifa96d5073b1341cab2a90e4dcd04752ee80c69bb
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Some stuff that was platform-specific is made common, and some repeated
code was made a macro. __in_section() is used elsewhere in the codebase
and its 2nd and 3rd arguments are not necessarily filename/counter.
GCC-specific stuff moved to the toolchain header.
Change-Id: Ibfae919b6dd8a77210801c14e9a1128b43bd63f6
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Hamming Weight or "popcount" consists in counting the number of bits set
to 1 in a particular word. This commit adds a macro to be able to use
the existing builtin for this purpose with the GCC compiler.
Change-Id: Iec64c19e897de2bc02e981071465bbe230ee9add
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
