Commit graph

42249 commits

Author SHA1 Message Date
Jukka Rissanen
601b972700 net: shell: Add command to print information about net_pkt
Print detailed information about a given net_pkt. This is
useful if there is a memory leak and you want to see more
detailed information about the data inside the buffer.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-05-08 13:24:42 +03:00
Kumar Gala
d20e06d08f tests: maxim_ds3231_api: Convert old DT syntax to new macros
Convert various DT_NORDIC_NRF_*LABEL to DT_LABEL(DT_NODELABEL())

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-08 05:21:58 -05:00
Kumar Gala
6693c1d8a1 tests: stream_flash: Convert old DT syntax to new macros
Convert DT_SOC_NV_FLASH_0_SIZE to DT_REG_SIZE()

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-08 05:21:58 -05:00
Stephanos Ioannidis
7778c22b60 soc: arm: atmel_sam: samv71: Remove ARM_MPU selection
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.

This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 11:11:59 +02:00
Stephanos Ioannidis
51a2655cca soc: arm: atmel_sam: same70: Remove ARM_MPU selection
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.

This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 11:11:59 +02:00
Stephanos Ioannidis
004039d08c tests: Rename kernel.fp_sharing
This commit renames the `kernel.fp_sharing` tests to
`kernel.fpu_sharing`, in order to align with the recent
`CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING` renaming.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00
Stephanos Ioannidis
728ce61968 tests: Rename kernel.common.stack_protection_arm_fp_sharing
This commit renames the `kernel.common.stack_protection_arm_fp_sharing`
test to `kernel.common.stack_protection_arm_fpu_sharing`, in order to
align with the recent `CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING`
renaming.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00
Stephanos Ioannidis
41a3d1e816 tests: Rename arch.arm.swap.common.fp_sharing
This commit renames the `arch.arm.swap.common.fp_sharing` tests to
`arch.arm.swap.common.fpu_sharing`, in order to align with the recent
`CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING` renaming.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00
Stephanos Ioannidis
0b930a2195 kconfig: Rename x86 FPU sharing symbols
This commit renames the x86 Kconfig `CONFIG_{EAGER,LAZY}_FP_SHARING`
symbol to `CONFIG_{EAGER,LAZY}_FPU_SHARING`, in order to align with the
recent `CONFIG_FP_SHARING` to `CONFIG_FPU_SHARING` renaming.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00
Stephanos Ioannidis
aaf93205bb kconfig: Rename CONFIG_FP_SHARING to CONFIG_FPU_SHARING
This commit renames the Kconfig `FP_SHARING` symbol to `FPU_SHARING`,
since this symbol specifically refers to the hardware FPU sharing
support by means of FPU context preservation, and the "FP" prefix is
not fully descriptive of that; leaving room for ambiguity.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 10:58:33 +02:00
Henrik Brix Andersen
4aeea753b2 samples: canbus: canopen: add program download support
Add optional program download support to the CANopen sample.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-05-08 10:53:42 +02:00
Henrik Brix Andersen
3c2984d4a9 scripts: west: add CANopen flash runner
Add west flash runner for program download via CANopen.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-05-08 10:53:42 +02:00
Henrik Brix Andersen
ed9f2fc28a samples: canbus: canopen: use python-can configuration file
Recommend setting up the python-can configuration file before running
the sample Python snippets and remove the GNU/Linux specific comment
from each snippet.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-05-08 10:53:42 +02:00
Henrik Brix Andersen
bbc1928dd1 canbus: canopen: add program download support
Add program download (firmware update) support according to the CAN in
Automation (CiA) 302-3 draft standard proposal v4.1.0.

The implementation supports a Zephyr specific vendor command allowing
external confirmation of a newly booted firmware image. If this is not
desired, the application can confirm the image by other means.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-05-08 10:53:42 +02:00
Anthony Brandon
28d5c0bfb7 boards: stm32f746g_disco: Update board doc for sdmmc
Add entries to features and pinmux tables to reflect support for sdmmc.

Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
2020-05-08 10:53:10 +02:00
Helge Juul
dc0c938359 boards: arm: stm32f746g_disco: enable sdmmc support
Update dtsi and pinmux macros for stm32f7 family. Add sdmmc1 to dts file
for stm32f746g_disco. Also add board specific configuration file for
fat_fs sample.

Signed-off-by: Helge Juul <helge@fastmail.com>
2020-05-08 10:53:10 +02:00
Anthony Brandon
cf89e9991d boards: stm32l496g_disco: Update board doc for sdmmc
Add entries to features and pinmux tables to reflect support for sdmmc.

Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
2020-05-08 10:53:10 +02:00
Anthony Brandon
a71f77e601 boards: arm: stm32l496g_disco: enable sdmmc support
Update the dtsi for stm32l471 (which the higher SoCs are based on) to
support the stm32-sdmmc disk access device. Enable the device for the
stm32l496g_disco board, and update the pinmuxing.
Note that the stm32l496g_disco board also has a card detect gpio
(MFX_GPIO8), but this is not supported yet. When not specified the
driver will assume a card is present.

Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
2020-05-08 10:53:10 +02:00
Anthony Brandon
631cad428b disk: add stm32 sdmmc disk access driver
Add a disk access driver for the stm32 sdmmc component. The driver is
based around the stm32 cube HAL and uses the blocking API.

Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
2020-05-08 10:53:10 +02:00
Bilal Wasim
54550c04eb net: qemu: Adding support for User Networking
Added support for Qemu User Networking and tested with
qemu_x86 model. The support is kept simple assuming that
the TAP interface will always be preferred for more
sophisticated / practical use cases.

QEMU User Networking is implemented using "slirp", which
provides a full TCP/IP stack within QEMU and uses that
stack to implement a virtual NAT'd network. As this
support is built into QEMU, it can be used with any model
and requires no admin privileges on the host machine,
unlike TAP.

Added documentation to facilitate the user.

Signed-off-by: Bilal Wasim <bilalwasim676@gmail.com>
2020-05-08 10:47:38 +02:00
Andy Ross
46dc8a0813 include: Add documentation for spinlocks
The kernel spinlock API didn't have proper API documentation.  Fix
that.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2020-05-08 10:46:44 +02:00
Abhishek Shah
012472f7d5 boards: arm: Add bcm958402m2_a72 board
Add support for bcm958402m2_a72 board for booting zephyr
on Cortex-A72 core.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-05-08 10:46:23 +02:00
Arjun Jyothi
4902c3ab2a boards: arm: Add bcm958402m2_m7 board
Add support for bcm958402m2_m7 board for booting zephyr
on Cortex-M7 core.

Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
2020-05-08 10:46:23 +02:00
Arjun Jyothi
d18ae2e9fb soc: arm: Add Broadcom Viper SoC support
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.

Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-05-08 10:46:23 +02:00
Abhishek Shah
2f85c01eaa arch: arm: aarch64: Add Cortex-A72 config
Add Cortex-A72 config in order to set "-mcpu" correctly.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-05-08 10:46:23 +02:00
Jukka Rissanen
ad9f32a4e9 net: lldp: Sent LLDP packet was missing proper net_pkt type
The LLDP packet was created but its type was not set to LLDP
and was sent as ARP message.

Fixes #25084

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-05-08 11:43:00 +03:00
Paul Sokolovsky
44e2a0343d samples: sockets: echo_async_select: Add CONFIG_POSIX_API config
Build a sample variant with CONFIG_POSIX_API enabled, to check that
we have select() call available to applications.

Also, bump stack size, as the app crashes now with the default size.

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2020-05-08 11:16:31 +03:00
Paul Sokolovsky
ecf8c0146d include: posix: Add <sys/select.h> header for POSIX subsystem
Provides implementation of select() call in terms of zsock_select().

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2020-05-08 11:16:31 +03:00
Robert Lubos
139da50e3c net: openthread: Allow to disable automatic network attachment
Add OpenThread configuration option, which allows to configure and start
OpenThread stack operation manually. This mode should be used in NCP
devices, as well as is needed for certification purposes, where
OpenTread stack have to be configured by the test framework and not
initialize and join the network on its own.

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2020-05-08 10:44:27 +03:00
Erwan Gouriou
f81c5547f2 boards: nucleo_l552ze_q: Set system clock to 110MHz
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
c4d9de1850 drivers/clock_control: stm32: msi: Enable MSI range config in PLL mode
When MSI clock is used a source of PLL, it should be possible to
select its frequency range. Fix this.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
6d31b1075a boards: Add support for nucleo_l552ze
Tested with hello_world, basic/blinky, basic/button.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
4b3d79f1bb drivers: stm32: Add pinmux headers for stm32l5
Copy/pasted from L4 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
1d3c1f8d2e drivers/serial: Add support for stm32l5 soc
Add serial support for STM32L5 serial driver and instances

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
cdd5856167 driver/gpio: stm32: Add STM32L5 support
Add basic GPIO support. Regarding interface with EXTI,
STM32L5 is similar to STM32G0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
1f054a7b31 drivers/exti: stm32: Add support for STM32L5 series
Add support for stm32l5 socs on stm32 external interrupts driver

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
f258199595 drivers/clock_control: Add clock_control on STM32L5 series
Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
25ac59685f dts/arm/st: Add l5 device tree basics and stm32l552x socs
Add l5 secure and non secure device tree files

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou
3057d801c7 soc/arm/st_stm32: Add stm32l5 series soc support
This provides basic stm32l5 series SoC support.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Jukka Rissanen
34b7a6c81c testsuite: Allow user to override minimal logging
The testsuite was always forcing minimal logging. This is problematic
as it does not allow user to see full logging string. Allow user to
override the minimal logging if needed, the default is still to
enable minimal logging.

Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
2020-05-07 23:47:55 -05:00
Krzysztof Chruscinski
2e6e818c91 tests: shell: Add test for raw argument option
Added test for commands with SHELL_OPT_ARG_RAW flag set.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-05-07 23:47:39 -05:00
Krzysztof Chruscinski
512de5ecac shell: Refactor command execution to enable raw arguments
Added special flag that can be used to indicate that optional
arguments are passed without any parsing (e.g. quotation marks
removal). Modified execute command to parse command line buffer
argument by argument.

After this change it is possible to forward whole command to
command handler (using select).

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2020-05-07 23:47:39 -05:00
Robert Lubos
2c2771970e modules: mbedtls: Update mbedTLS commit and apply fixes
Update mbedTLS commit along with the following fixes:

* Fix naming inconsistencies in some cipher modes, to match core mbedTLS
  configs
* Add Kconfig to enable CTR cipher mode

Fixes #22421

Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
2020-05-07 23:46:08 -05:00
Hans Wilmers
fdd89efd3a drivers: modem: ublox-sara-r4: automatic setting of APN
During communication initialisation, the IMSI of the inserted SIM
card is evaluated to determine the APN. This is done by comparing
the first 5 characters of the IMSI to a list of known providers.
The list can be given in Kconfig.

To enable this functionality, set following bool in Kconfig:
MODEM_UBLOX_SARA_AUTODETECT_APN

To set a list of providers, set following string:
MODEM_UBLOX_SARA_AUTODETECT_APN_PROFILES

If the provider can not be found in the list, the APN given in
following entry is used as a fallback:
MODEM_UBLOX_SARA_R4_APN

Signed-off-by: Hans Wilmers <hans@wilmers.no>
2020-05-07 23:36:10 -05:00
Hans Wilmers
cef334b5fe drivers: modem: ublox-sara-r4: automatic detection of modem type
The modem type (Sara R410 or Sara U201) is detected automatically after
hardware initialisation of the modem. Further initialisation and
functionality is then chosen depending on the detected modem type.

To enable this functionality, set following bool in Kconfig:
MODEM_UBLOX_SARA_AUTODETECT_VARIANT

Signed-off-by: Hans Wilmers <hans@wilmers.no>
2020-05-07 23:36:10 -05:00
Stephanos Ioannidis
25fe4bf9c7 tests: drivers: Add console driver test
This commit adds the initial implementation of the console driver test.

The purpose of this test is to verify the output functionality of the
various types of console drivers (UART and semihost console types are
supported for now).

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-07 23:33:38 -05:00
Stephanos Ioannidis
2c00c8e504 cmake: emu: Support QEMU semihosting console emulation
The QEMU '-semihosting' option enables the emulation of the semihosting
mechanism that can be used to interface the Zephyr RTOS to the host
operating system.

In order to support semihosting console output, the QEMU semihosting
feature is enabled and its console is connected to the console backend
chardev.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-07 23:33:38 -05:00
ZhongYao Luo
1811fff2dd console: Add semihosting console
Many chips have only one serial port. When the serial port is occupied
by other devices, there is a lack of a console to output debugging
information. Semihosting can provide a console. The disadvantage of
semihosting is that a debugger must be connected, so it can only be
used for online debugging.

Signed-off-by: ZhongYao Luo <LuoZhongYao@gmail.com>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2020-05-07 23:33:38 -05:00
Johann Fischer
8c051f0809 boards: decawave_dwm1001_dev: enable DW1000 802154 driver
Enable DW1000 802154 driver.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2020-05-07 23:30:58 -05:00
Johann Fischer
d461befc2b boards: decawave_dwm1001_dev: add jlink runner support
Add jlink runner support.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2020-05-07 23:30:58 -05:00