michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: intel_adsp: Unify bootloader configuration

Browse source 
The generic bootloader code used a per-device "platform.h" file
imported from SOF.  These turn out to have very little actual content.
Move them to the core directory in a single header for now, pending
some rework to place the settings in devicetree.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-09-05 15:27:56 -07:00 • committed by Anas Nashif
commit ff1ccbd83c
7 changed files with 39 additions and 116 deletions
Download patch file Download diff file Expand all files Collapse all files

25
soc/xtensa/intel_adsp/cavs_v15/include/soc/platform.h
View file

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0
*
* Copyright(c) 2016 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/
#ifndef __PLATFORM_PLATFORM_H__
#define __PLATFORM_PLATFORM_H__
#define PLATFORM_RESET_MHE_AT_BOOT 1
#define PLATFORM_DISABLE_L2CACHE_AT_BOOT 1
#define PLATFORM_PRIMARY_CORE_ID 0
#define MAX_CORE_COUNT 2
#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
#error "Invalid core count - exceeding core limit"
#endif
#endif /* __PLATFORM_PLATFORM_H__ */

29
soc/xtensa/intel_adsp/cavs_v18/include/soc/platform.h
View file

@ -1,29 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0
*
* Copyright(c) 2016 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/
#ifndef __PLATFORM_PLATFORM_H__
#define __PLATFORM_PLATFORM_H__
#define PLATFORM_RESET_MHE_AT_BOOT 1
#define PLATFORM_MEM_INIT_AT_BOOT 1
#define PLATFORM_PRIMARY_CORE_ID 0
#define MAX_CORE_COUNT 4
#define PLATFORM_HPSRAM_EBB_COUNT 47
#define EBB_SEGMENT_SIZE 32
#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
#error "Invalid core count - exceeding core limit"
#endif
#endif /* __PLATFORM_PLATFORM_H__ */

30
soc/xtensa/intel_adsp/cavs_v20/include/soc/platform.h
View file

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0
*
* Copyright(c) 2017 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
* Rander Wang <rander.wang@intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/
#ifndef __PLATFORM_PLATFORM_H__
#define __PLATFORM_PLATFORM_H__
#define PLATFORM_RESET_MHE_AT_BOOT 1
#define PLATFORM_MEM_INIT_AT_BOOT 1
#define PLATFORM_PRIMARY_CORE_ID 0
#define MAX_CORE_COUNT 4
#define PLATFORM_HPSRAM_EBB_COUNT 47
#define EBB_SEGMENT_SIZE 32
#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
#error "Invalid core count - exceeding core limit"
#endif
#endif /* __PLATFORM_PLATFORM_H__ */

30
soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h
View file

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0
*
* Copyright(c) 2017 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
* Keyon Jie <yang.jie@linux.intel.com>
* Rander Wang <rander.wang@intel.com>
* Xiuli Pan <xiuli.pan@linux.intel.com>
*/
#ifndef __PLATFORM_PLATFORM_H__
#define __PLATFORM_PLATFORM_H__
#define PLATFORM_RESET_MHE_AT_BOOT 1
#define PLATFORM_MEM_INIT_AT_BOOT 1
#define PLATFORM_PRIMARY_CORE_ID 0
#define MAX_CORE_COUNT 4
#define PLATFORM_HPSRAM_EBB_COUNT 30
#define EBB_SEGMENT_SIZE 32
#if PLATFORM_CORE_COUNT > MAX_CORE_COUNT
#error "Invalid core count - exceeding core limit"
#endif
#endif /* __PLATFORM_PLATFORM_H__ */

4
soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
View file

@ -16,10 +16,12 @@
#include <devicetree.h>
#include <soc/shim.h>
#include <cavs-shim.h>
#include <soc/platform.h>
#include <soc/memory.h>
#include <xtensa/corebits.h>
#include <xtensa/config/core-isa.h>
#include "platform.h"
#define PLATFORM_PRIMARY_CORE_ID 0
#define SHIM_ADDR DT_REG_ADDR(DT_NODELABEL(shim))
#define SHIM_L2_MECS (SHIM_ADDR + 0xd0)

2
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
View file

@ -11,13 +11,13 @@
#include <stdint.h>
#include <cavs/version.h>
#include <soc/platform.h>
#include <soc/memory.h>
#include <soc/shim.h>
#include <adsp/io.h>
#include <soc.h>
#include <arch/xtensa/cache.h>
#include <cavs-shim.h>
#include "platform.h"
#include "manifest.h"
#if CONFIG_SOC_INTEL_S1000

35
soc/xtensa/intel_adsp/common/bootloader/platform.h Normal file
View file

@ -0,0 +1,35 @@
/* SPDX-License-Identifier: Apache-2.0
* Copyright (c) 2021 Intel Corporation. All rights reserved.
*/
#ifndef ZEPHYR_INCLUDE_INTEL_ADSP_PLATFORM_H_
#define ZEPHYR_INCLUDE_INTEL_ADSP_PLATFORM_H_
/* Various cAVS platform dependencies needed by the bootloader code.
* These probably want to migrate to devicetree.
*/
#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V25)
#define PLATFORM_RESET_MHE_AT_BOOT
#define PLATFORM_MEM_INIT_AT_BOOT
#define PLATFORM_HPSRAM_EBB_COUNT 30
#define EBB_SEGMENT_SIZE 32
#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V20)
#define PLATFORM_RESET_MHE_AT_BOOT
#define PLATFORM_MEM_INIT_AT_BOOT
#define PLATFORM_HPSRAM_EBB_COUNT 47
#define EBB_SEGMENT_SIZE 32
#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18)
#define PLATFORM_RESET_MHE_AT_BOOT
#define PLATFORM_MEM_INIT_AT_BOOT
#define PLATFORM_HPSRAM_EBB_COUNT 47
#define EBB_SEGMENT_SIZE 32
#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
#define PLATFORM_RESET_MHE_AT_BOOT
#define PLATFORM_DISABLE_L2CACHE_AT_BOOT
#endif
#endif /* ZEPHYR_INCLUDE_INTEL_ADSP_PLATFORM_H_ */