ff1ccbd83c
The generic bootloader code used a per-device "platform.h" file imported from SOF. These turn out to have very little actual content. Move them to the core directory in a single header for now, pending some rework to place the settings in devicetree. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
232 lines
4.1 KiB
ArmAsm
232 lines
4.1 KiB
ArmAsm
/*
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* Copyright(c) 2016 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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*/
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/*
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* Entry point from ROM - assumes :-
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*
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* 1) C runtime environment is initialized by ROM.
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* 2) Stack is in first HPSRAM bank.
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*/
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#include <devicetree.h>
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#include <soc/shim.h>
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#include <cavs-shim.h>
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#include <soc/memory.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/core-isa.h>
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#include "platform.h"
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#define PLATFORM_PRIMARY_CORE_ID 0
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#define SHIM_ADDR DT_REG_ADDR(DT_NODELABEL(shim))
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#define SHIM_L2_MECS (SHIM_ADDR + 0xd0)
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#define SHIM_L2_PREF_CFG (SHIM_ADDR + 0x508)
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.type boot_master_core, @function
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.begin literal_prefix .boot_entry
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.section .boot_entry.text, "ax"
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.align 4
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.global boot_entry
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boot_entry:
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entry a1, 48
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j boot_init
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.align 4
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.literal_position
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#if defined(PLATFORM_RESET_MHE_AT_BOOT)
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l2_mecs:
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.word SHIM_L2_MECS
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#endif
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#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
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l2_cache_pref:
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.word SHIM_L2_PREF_CFG
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#endif
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sof_stack_base:
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.word SOF_STACK_BASE
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wnd0_base:
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.word DMWBA(0)
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wnd0_size:
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.word DMWLO(0)
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wnd0_base_val:
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.word HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE
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wnd0_size_val:
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.word HP_SRAM_WIN0_SIZE | 0x7
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wnd0_status_address:
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.word HP_SRAM_WIN0_BASE
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wnd0_error_address:
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.word HP_SRAM_WIN0_BASE | 0x4
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#if defined(PLATFORM_MEM_INIT_AT_BOOT)
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shim_ldoctl_address:
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.word (SHIM_ADDR + 0xa4)
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ldoctl_hpsram_ldo_on:
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.word SHIM_LDOCTL_HPSRAM_LDO_ON
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ldoctl_hpsram_ldo_bypass:
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.word SHIM_LDOCTL_HPSRAM_LDO_BYPASS
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hspgctl0_address:
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.word HSPGCTL0
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hsrmctl0_address:
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.word HSRMCTL0
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hspgctl1_address:
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.word HSPGCTL1
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hsrmctl1_address:
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.word HSRMCTL1
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hspgists0_address:
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.word HSPGISTS0
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hspgists1_address:
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.word HSPGISTS1
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#endif
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fw_loaded_status_value:
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.word 0x00000005
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fw_no_errors_value:
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.word 0x00000000
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boot_init:
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.align 4
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#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
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l32r a3, l2_cache_pref
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movi a5, 0
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s32i a5, a3, 0
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memw
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#endif
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#if defined(PLATFORM_RESET_MHE_AT_BOOT)
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/* reset memory hole */
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l32r a3, l2_mecs
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movi a5, 0
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s32i a5, a3, 0
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#endif
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#if defined(PLATFORM_MEM_INIT_AT_BOOT)
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/* turn on memory _before_ stack reprogramming */
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l32r a3, ldoctl_hpsram_ldo_on
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l32r a5, shim_ldoctl_address
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s32i a3, a5, 0
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memw
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/* delay for 256 iterations before touching pwr regs */
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movi a2, 256
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1: addi.n a2, a2, -1
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bnez a2, 1b
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movi a3, 0
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l32r a5, hspgctl0_address
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s32i a3, a5, 0
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memw
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l32r a5, hsrmctl0_address
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s32i a3, a5, 0
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memw
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l32r a5, hspgctl1_address
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s32i a3, a5, 0
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memw
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l32r a5, hsrmctl1_address
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s32i a3, a5, 0
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memw
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/* wait for status of first bank group */
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l32r a5, hspgists0_address
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2:
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l32i a3, a5, 0
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bnez a3, 2b
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/* wait for status of second bank group */
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l32r a5, hspgists1_address
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3:
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l32i a3, a5, 0
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bnez a3, 3b
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/* delay for 256 iterations before touching pwr regs */
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movi a2, 256
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4: addi.n a2, a2, -1
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bnez a2, 4b
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l32r a3, ldoctl_hpsram_ldo_bypass
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l32r a5, shim_ldoctl_address
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s32i a3, a5, 0
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memw
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#endif
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/* reprogram stack to the area defined by main FW */
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l32r a3, sof_stack_base
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mov sp, a3
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/* set status register to 0x00000005 in wnd0 */
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l32r a3, fw_loaded_status_value
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l32r a5, wnd0_status_address
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s32i a3, a5, 0
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/* set error register to 0x00 in wnd0 */
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l32r a3, fw_no_errors_value
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l32r a5, wnd0_error_address
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s32i a3, a5, 0
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/* realloc memory window0 to
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continue reporting boot progress */
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l32r a3, wnd0_size
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l32r a5, wnd0_size_val
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s32i a5, a3, 0
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memw
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l32r a3, wnd0_base
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l32r a5, wnd0_base_val
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s32i a5, a3, 0
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memw
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#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \
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XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
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/* Enable zero-overhead loop instr buffer,
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and snoop responses, if configured. */
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movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN)
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rsr a2, MEMCTL
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or a2, a2, a3
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wsr a2, MEMCTL
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#endif
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/* determine core we are running on */
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rsr.prid a2
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movi a3, PLATFORM_PRIMARY_CORE_ID
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beq a2, a3, 1f
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/* no core should get here */
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j dead
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1:
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/* we are primary core so boot it */
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call8 boot_master_core
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dead:
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/* should never get here - we are dead */
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j dead
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.size boot_entry, . - boot_entry
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.end literal_prefix
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