diff --git a/soc/arm/atmel_sam0/common/soc_samd5x.c b/soc/arm/atmel_sam0/common/soc_samd5x.c
index 7b7d8220c1a..e680163202f 100644
--- a/soc/arm/atmel_sam0/common/soc_samd5x.c
+++ b/soc/arm/atmel_sam0/common/soc_samd5x.c
@@ -117,8 +117,14 @@ void z_arm_platform_init(void)
 		dfll_div = 1;
 	}
 
-	/* enable the Cortex M Cache Controller */
-	CMCC->CTRL.bit.CEN = 1;
+	/*
+	 * Force Cortex M Cache Controller disabled
+	 *
+	 * It is not clear if regular Cortex-M instructions can be used to
+	 * perform cache maintenance or this is a proprietary cache controller
+	 * that require special SoC support.
+	 */
+	CMCC->CTRL.bit.CEN = 0;
 
 	gclk_reset();
 	osc32k_init();