michaelh/zephyr
1
0
Fork 0
Code Releases Activity

cavs: remove unused and dangerous definitions

Browse source 
uncache_to_cache(), cache_to_uncache() and is_uncached() macros
are currently unused in Zephyr, besides the former two are
dangerous because they add and subtract an offset instead of
masking and unmasking a bit, which can lead to wrong addresses
if applied repeatedly. Remove these macros for now, we can
re-add them later if needed in their fixed versions.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2021-04-29 15:26:30 +02:00 • committed by Anas Nashif
commit e027a54440
4 changed files with 0 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

8
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -140,14 +140,6 @@
#define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_MASK 0xFF000000
#define SRAM_ALIAS_OFFSET 0x20000000 #define SRAM_ALIAS_OFFSET 0x20000000
#define uncache_to_cache(address) \
((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
#define cache_to_uncache(address) \
((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
#define is_uncached(address) \
(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
/* shim */ /* shim */
#define SHIM_BASE 0x00001000 #define SHIM_BASE 0x00001000
#define SHIM_SIZE 0x00000100 #define SHIM_SIZE 0x00000100

8
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -137,14 +137,6 @@
#define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_MASK 0xFF000000
#define SRAM_ALIAS_OFFSET 0x20000000 #define SRAM_ALIAS_OFFSET 0x20000000
#define uncache_to_cache(address) \
((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
#define cache_to_uncache(address) \
((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
#define is_uncached(address) \
(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
/* shim */ /* shim */
#define SHIM_BASE 0x00071F00 #define SHIM_BASE 0x00071F00
#define SHIM_SIZE 0x00000100 #define SHIM_SIZE 0x00000100

8
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -137,14 +137,6 @@
#define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_MASK 0xFF000000
#define SRAM_ALIAS_OFFSET 0x20000000 #define SRAM_ALIAS_OFFSET 0x20000000
#define uncache_to_cache(address) \
((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
#define cache_to_uncache(address) \
((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
#define is_uncached(address) \
(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
/* shim */ /* shim */
#define SHIM_BASE 0x00071F00 #define SHIM_BASE 0x00071F00
#define SHIM_SIZE 0x00000100 #define SHIM_SIZE 0x00000100

8
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -139,14 +139,6 @@
#define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_MASK 0xFF000000
#define SRAM_ALIAS_OFFSET 0x20000000 #define SRAM_ALIAS_OFFSET 0x20000000
#define uncache_to_cache(address) \
((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
#define cache_to_uncache(address) \
((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
#define is_uncached(address) \
(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
/* shim */ /* shim */
#define SHIM_BASE 0x00071F00 #define SHIM_BASE 0x00071F00
#define SHIM_SIZE 0x00000100 #define SHIM_SIZE 0x00000100