diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
index c078f46a080..37f54ed131f 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
@@ -140,14 +140,6 @@
 #define SRAM_ALIAS_MASK		0xFF000000
 #define SRAM_ALIAS_OFFSET	0x20000000
 
-
-#define uncache_to_cache(address) \
-	((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
-#define cache_to_uncache(address) \
-	((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
-#define is_uncached(address) \
-	(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
-
 /* shim */
 #define SHIM_BASE		0x00001000
 #define SHIM_SIZE		0x00000100
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
index dc86226fb46..ab8302d1fc3 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
@@ -137,14 +137,6 @@
 #define SRAM_ALIAS_MASK		0xFF000000
 #define SRAM_ALIAS_OFFSET	0x20000000
 
-
-#define uncache_to_cache(address) \
-	((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
-#define cache_to_uncache(address) \
-	((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
-#define is_uncached(address) \
-	(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
-
 /* shim */
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
index cc79f622038..0ffcebc39ba 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -137,14 +137,6 @@
 #define SRAM_ALIAS_MASK		0xFF000000
 #define SRAM_ALIAS_OFFSET	0x20000000
 
-
-#define uncache_to_cache(address) \
-	((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
-#define cache_to_uncache(address) \
-	((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
-#define is_uncached(address) \
-	(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
-
 /* shim */
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
index a7f50eacfd3..7751ef6078a 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -139,14 +139,6 @@
 #define SRAM_ALIAS_MASK		0xFF000000
 #define SRAM_ALIAS_OFFSET	0x20000000
 
-
-#define uncache_to_cache(address) \
-	((__typeof__(address))((uint32_t)(address) + SRAM_ALIAS_OFFSET))
-#define cache_to_uncache(address) \
-	((__typeof__(address))((uint32_t)(address) - SRAM_ALIAS_OFFSET))
-#define is_uncached(address) \
-	(((uint32_t)(address) & SRAM_ALIAS_MASK) == SRAM_ALIAS_BASE)
-
 /* shim */
 #define SHIM_BASE		0x00071F00
 #define SHIM_SIZE		0x00000100