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stm32f1: Enable STM32Cube SDK support on stm32f1 family

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Create HAS_CUBE config flag to control activation of STM32Cube support.
Generate fitting compilation options for STM32Cube in
/ext/hal/stm32cube/Makefile soc.h is updated to include minimum include
files from ext/hal/stm23cube

Change-Id: If58ce0a4fdb7fbf5f171dfe5f1f8eb75126a8313
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Erwan Gouriou 2016-11-02 09:58:02 +01:00 • committed by Kumar Gala
commit dc70dc0977
3 changed files with 34 additions and 33 deletions
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1
arch/arm/soc/st_stm32/stm32f1/Kconfig.series
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@ -21,5 +21,6 @@ config SOC_SERIES_STM32F1X
select CPU_CORTEX_M3
select SOC_FAMILY_STM32
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select HAS_STM32CUBE
help
Enable support for STM32F1 MCU series

40
arch/arm/soc/st_stm32/stm32f1/soc.h
View file

@ -28,51 +28,25 @@
#ifndef _STM32F1_SOC_H_
#define _STM32F1_SOC_H_
/* peripherals start address */
#define PERIPH_BASE 0x40000000
/* use naming consistent with STMF10x Peripherals Library */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define GPIO_REG_SIZE 0x400
/* base address for where GPIO registers start */
#define GPIO_PORTS_BASE (GPIOA_BASE)
/* FIXME: keep these defines until we enable STM32CUBE on this family */
/* Then they will bre replaced by "USARTX_BASE" defines */
/* UART */
#define USART1_ADDR (APB2PERIPH_BASE + 0x3800)
#define USART2_ADDR (APB1PERIPH_BASE + 0x4400)
#define USART3_ADDR (APB1PERIPH_BASE + 0x4800)
/* Reset and Clock Control */
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define GPIO_REG_SIZE 0x400
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
/* base address for where GPIO registers start */
#define GPIO_PORTS_BASE (GPIOA_BASE)
/* EXTI */
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
/* AFIO */
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
/* IWDG */
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
/* FLASH */
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
#ifndef _ASMLANGUAGE
#include <device.h>
#include <misc/util.h>
#include <drivers/rand32.h>
#include <stm32f1xx.h>
/* IO pin functions */
enum stm32f10x_pin_config_mode {
STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,