diff --git a/arch/arm/soc/st_stm32/stm32f1/Kconfig.series b/arch/arm/soc/st_stm32/stm32f1/Kconfig.series
index 54f98d8761e..7e63896bf5d 100644
--- a/arch/arm/soc/st_stm32/stm32f1/Kconfig.series
+++ b/arch/arm/soc/st_stm32/stm32f1/Kconfig.series
@@ -21,5 +21,6 @@ config SOC_SERIES_STM32F1X
 	select CPU_CORTEX_M3
 	select SOC_FAMILY_STM32
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
 	help
 	 Enable support for STM32F1 MCU series
diff --git a/arch/arm/soc/st_stm32/stm32f1/soc.h b/arch/arm/soc/st_stm32/stm32f1/soc.h
index e009c2d3b4f..41c9e1b5919 100644
--- a/arch/arm/soc/st_stm32/stm32f1/soc.h
+++ b/arch/arm/soc/st_stm32/stm32f1/soc.h
@@ -28,51 +28,25 @@
 #ifndef _STM32F1_SOC_H_
 #define _STM32F1_SOC_H_
 
-/* peripherals start address */
-#define PERIPH_BASE           0x40000000
-
-/* use naming consistent with STMF10x Peripherals Library */
-#define APB1PERIPH_BASE        PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
 
+/* FIXME: keep these defines until we enable STM32CUBE on this family */
+/* Then they will bre replaced by "USARTX_BASE" defines */
 /* UART */
 #define USART1_ADDR           (APB2PERIPH_BASE + 0x3800)
 #define USART2_ADDR           (APB1PERIPH_BASE + 0x4400)
 #define USART3_ADDR           (APB1PERIPH_BASE + 0x4800)
 
-/* Reset and Clock Control */
-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
-
-#define GPIO_REG_SIZE         0x400
-#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
-/* base address for where GPIO registers start */
-#define GPIO_PORTS_BASE       (GPIOA_BASE)
-
-/* EXTI */
-#define EXTI_BASE            (APB2PERIPH_BASE + 0x0400)
-
-/* AFIO */
-#define AFIO_BASE            (APB2PERIPH_BASE + 0x0000)
-
-/* IWDG */
-#define IWDG_BASE            (APB1PERIPH_BASE + 0x3000)
-
-/* FLASH */
-#define FLASH_R_BASE           (AHBPERIPH_BASE + 0x2000)
-
 #ifndef _ASMLANGUAGE
 
 #include <device.h>
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
+#include <stm32f1xx.h>
+
 /* IO pin functions */
 enum stm32f10x_pin_config_mode {
 	STM32F10X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
diff --git a/ext/hal/st/stm32cube/Makefile b/ext/hal/st/stm32cube/Makefile
index c83870ff0aa..79ca173a93b 100644
--- a/ext/hal/st/stm32cube/Makefile
+++ b/ext/hal/st/stm32cube/Makefile
@@ -1,5 +1,31 @@
+# Makefile - STM32Cube SDK
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
 ifdef CONFIG_HAS_STM32CUBE
 
+STM32CUBE_CPU = $(shell echo $(CONFIG_SOC) | tr '[a-wyz]' '[A-WYZ]')
+
+# STM32Cub uses the CPU name to expose SOC-specific attributes of a specific
+# peripheral.
+# It also requires USE_HAL_DRIVER to be define in order to benefit from
+# STM32Cube HAL and LL APIs
+
+KBUILD_CFLAGS += -D$(STM32CUBE_CPU) -DUSE_HAL_DRIVER
+
 ifdef CONFIG_SOC_SERIES_STM32F1X
 ZEPHYRINCLUDE += -I$(srctree)/ext/hal/st/stm32cube/stm32f1xx/soc/
 ZEPHYRINCLUDE += -I$(srctree)/ext/hal/st/stm32cube/stm32f1xx/drivers/include/