michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: clock_control: Add STM32G4X clock support

Browse source 
Add clock support for STM32G4X SoC series.

Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
This commit is contained in:
Richard Osterloh 2019-09-04 09:37:52 +01:00 • committed by Andrew Boie
commit ca7cbb5a08
8 changed files with 158 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

26
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -91,22 +91,26 @@ static inline int stm32_clock_control_on(struct device *dev,
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
CONFIG_SOC_SERIES_STM32F7X */
CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32F2X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
@ -139,22 +143,25 @@ static inline int stm32_clock_control_off(struct device *dev,
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X)
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
CONFIG_SOC_SERIES_STM32F7X */
CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32G4X */
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_DisableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr);
@ -205,7 +212,8 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
case STM32_CLOCK_BUS_APB1:
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2:
#endif
*rate = apb1_clock;