diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index c73a5ac4c47..a9f445b132f 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -28,5 +28,6 @@ else()
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)
   zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c)
+  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c)
 endif()
 endif()
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index e40150dc334..3d55090697c 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -126,6 +126,7 @@ source "drivers/clock_control/Kconfig.stm32h7"
 source "drivers/clock_control/Kconfig.stm32l0_l1"
 source "drivers/clock_control/Kconfig.stm32l4_wb"
 source "drivers/clock_control/Kconfig.stm32g0"
+source "drivers/clock_control/Kconfig.stm32g4"
 
 # Bus clocks configuration options
 
diff --git a/drivers/clock_control/Kconfig.stm32g4 b/drivers/clock_control/Kconfig.stm32g4
new file mode 100644
index 00000000000..cfe9d364188
--- /dev/null
+++ b/drivers/clock_control/Kconfig.stm32g4
@@ -0,0 +1,56 @@
+# Kconfig - STM32G4 PLL configuration options
+#
+# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+#
+#  SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32G4X
+
+config CLOCK_STM32_PLL_M_DIVISOR
+	int "PLL divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 4
+	range 1 16
+	help
+	  PLL divisor, allowed values: 1-16.
+
+config CLOCK_STM32_PLL_N_MULTIPLIER
+	int "PLL multiplier"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 75
+	range 8 127
+	help
+	  PLL multiplier, allowed values: 8-127.
+
+config CLOCK_STM32_PLL_P_DIVISOR
+	int "PLL P Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 7
+	range 7 17
+	help
+	  PLL P Output divisor, allowed values: 7, 17.
+
+config CLOCK_STM32_PLL_Q_DIVISOR
+	int "PLL Q Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 8
+	help
+	  PLL Q Output divisor, allowed values: 2, 4, 6, 8.
+
+config CLOCK_STM32_PLL_R_DIVISOR
+	int "PLL R Divisor"
+	depends on CLOCK_STM32_SYSCLK_SRC_PLL
+	default 2
+	range 2 8
+	help
+	  PLL R Output divisor, allowed values: 2, 4, 6, 8.
+
+config CLOCK_STM32_LSE
+	bool "Low-speed external clock"
+	help
+	  Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
+	  crystal resonator oscillator.
+
+endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index 61a8ebbabc9..2c7693b5854 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -91,22 +91,26 @@ static inline int stm32_clock_control_on(struct device *dev,
 	defined(CONFIG_SOC_SERIES_STM32F4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F7X) || \
 	defined(CONFIG_SOC_SERIES_STM32F2X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	case STM32_CLOCK_BUS_AHB2:
 		LL_AHB2_GRP1_EnableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
-		CONFIG_SOC_SERIES_STM32F7X */
+		CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32F2X ||
+		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
 	case STM32_CLOCK_BUS_APB1:
 		LL_APB1_GRP1_EnableClock(pclken->enr);
 		break;
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F0X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	case STM32_CLOCK_BUS_APB1_2:
 		LL_APB1_GRP2_EnableClock(pclken->enr);
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
+		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
 #if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_APB2:
 		LL_APB2_GRP1_EnableClock(pclken->enr);
@@ -139,22 +143,25 @@ static inline int stm32_clock_control_off(struct device *dev,
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F7X) || \
-	defined(CONFIG_SOC_SERIES_STM32F2X)
+	defined(CONFIG_SOC_SERIES_STM32F2X) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	case STM32_CLOCK_BUS_AHB2:
 		LL_AHB2_GRP1_DisableClock(pclken->enr);
 		break;
 #endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
-		CONFIG_SOC_SERIES_STM32F7X */
+		CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32G4X */
 	case STM32_CLOCK_BUS_APB1:
 		LL_APB1_GRP1_DisableClock(pclken->enr);
 		break;
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F0X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	case STM32_CLOCK_BUS_APB1_2:
 		LL_APB1_GRP2_DisableClock(pclken->enr);
 		break;
-#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
+#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
+		CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
 #if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
 	case STM32_CLOCK_BUS_APB2:
 		LL_APB2_GRP1_DisableClock(pclken->enr);
@@ -205,7 +212,8 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
 	case STM32_CLOCK_BUS_APB1:
 #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F0X) || \
-	defined(CONFIG_SOC_SERIES_STM32WBX)
+	defined(CONFIG_SOC_SERIES_STM32WBX) || \
+	defined(CONFIG_SOC_SERIES_STM32G4X)
 	case STM32_CLOCK_BUS_APB1_2:
 #endif
 		*rate = apb1_clock;
diff --git a/drivers/clock_control/clock_stm32g4.c b/drivers/clock_control/clock_stm32g4.c
new file mode 100644
index 00000000000..9df6d7335aa
--- /dev/null
+++ b/drivers/clock_control/clock_stm32g4.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <soc.h>
+#include <drivers/clock_control.h>
+#include <sys/util.h>
+#include <clock_control/stm32_clock_control.h>
+#include "clock_stm32_ll_common.h"
+
+
+#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
+
+/* Macros to fill up division factors values */
+#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
+#define pllm(v) z_pllm(v)
+
+#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
+#define pllr(v) z_pllr(v)
+
+/**
+ * @brief fill in pll configuration structure
+ */
+void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
+{
+	pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
+	pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
+	pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
+}
+#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
+
+/**
+ * @brief Activate default clocks
+ */
+void config_enable_default_clocks(void)
+{
+#ifdef CONFIG_CLOCK_STM32_LSE
+	/* LSE belongs to the back-up domain, enable access.*/
+
+	/* Enable the power interface clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+
+	/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
+	LL_PWR_EnableBkUpAccess();
+	while (!LL_PWR_IsEnabledBkUpAccess()) {
+		/* Wait for Backup domain access */
+	}
+
+	/* Enable LSE Oscillator (32.768 kHz) */
+	LL_RCC_LSE_Enable();
+	while (!LL_RCC_LSE_IsReady()) {
+		/* Wait for LSE ready */
+	}
+
+	LL_PWR_DisableBkUpAccess();
+#endif
+}
+
+/**
+ * @brief Function kept for driver genericity
+ */
+void LL_RCC_MSI_Disable(void)
+{
+	/* Do nothing */
+}
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
index fba1bc54baa..0ac076fef06 100644
--- a/dts/arm/st/g4/stm32g4.dtsi
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -6,6 +6,7 @@
 
 
 #include <arm/armv7-m.dtsi>
+#include <dt-bindings/clock/stm32_clock.h>
 
 / {
 	cpus {
@@ -24,6 +25,12 @@
 	};
 
 	soc {
+		rcc: rcc@40021000 {
+			compatible = "st,stm32-rcc";
+			#clock-cells = <2>;
+			reg = <0x40021000 0x400>;
+			label = "STM32_CLK_RCC";
+		};
 
 	};
 
diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.series
index f8e34eadb38..eba83d28f15 100644
--- a/soc/arm/st_stm32/stm32g4/Kconfig.series
+++ b/soc/arm/st_stm32/stm32g4/Kconfig.series
@@ -12,5 +12,6 @@ config SOC_SERIES_STM32G4X
 	select SOC_FAMILY_STM32
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
 	help
 	  Enable support for STM32G4 MCU series
diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h
index 1a82d4d14cf..f4832aaa893 100644
--- a/soc/arm/st_stm32/stm32g4/soc.h
+++ b/soc/arm/st_stm32/stm32g4/soc.h
@@ -27,6 +27,13 @@
 /* Add include for DTS generated information */
 #include <generated_dts_board.h>
 
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32g4xx_ll_utils.h>
+#include <stm32g4xx_ll_bus.h>
+#include <stm32g4xx_ll_rcc.h>
+#include <stm32g4xx_ll_system.h>
+#include <stm32g4xx_ll_pwr.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32G4_SOC_H_ */