soc: arm: nxp_imx: rt: Remove CONFIG_OCRAM_NOCACHE setting

Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

doc/releases/release-notes-3.5.rst

@@ -97,6 +97,8 @@ Boards & SoC Support
   * i.MX RT SOCs no longer enable CONFIG_DEVICE_CONFIGURATION_DATA by default.
     boards using external SDRAM should set CONFIG_DEVICE_CONFIGURATION_DATA
     and CONFIG_NXP_IMX_EXTERNAL_SDRAM to enabled.
+  * i.MX RT SOCs no longer support CONFIG_OCRAM_NOCACHE, as this functionality
+    can be achieved using devicetree memory regions
 
 * Added support for these ARC boards:
 

soc/arm/nxp_imx/rt/CMakeLists.txt

@@ -11,7 +11,6 @@ zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER
 
 # Add custom mpu regions
 zephyr_sources(mpu_regions.c)
-zephyr_linker_sources_ifdef(CONFIG_OCRAM_NOCACHE SECTIONS sections.ld)
 
 zephyr_linker_section_configure(
   SECTION .rom_start

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -787,14 +787,6 @@ config CODE_OCRAM
 
 endchoice
 
-config OCRAM_NOCACHE
-	bool "Create noncacheable OCRAM region"
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	select PLATFORM_SPECIFIC_INIT
-	help
-	  Creates linker section and MPU region for OCRAM region with
-	  noncacheable attribute. OCRAM memory is useful for fast DMA transfers.
-
 config NXP_IMX_EXTERNAL_SDRAM
 	bool "Allow access to external SDRAM region"
 	help

soc/arm/nxp_imx/rt/mpu_regions.c

@@ -9,35 +9,20 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/devicetree/memory-attr.h>
 #include "../../common/cortex_m/arm_mpu_mem_cfg.h"
-#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
 
 static const struct arm_mpu_region mpu_regions[] = {
 	/* Region 0 */
 	MPU_REGION_ENTRY("FLASH_0",
 			 CONFIG_FLASH_BASE_ADDRESS,
 			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
-#if IS_CHOSEN_SRAM(ocram)
-	/* Mark SRAM as noncacheable */
-	/* Region 1 */
-	MPU_REGION_ENTRY("SRAM_0",
-			 CONFIG_SRAM_BASE_ADDRESS,
-			 REGION_RAM_NOCACHE_ATTR(REGION_SRAM_SIZE)),
-
-#else
 	/* Region 1 */
 	MPU_REGION_ENTRY("SRAM_0",
 			 CONFIG_SRAM_BASE_ADDRESS,
 			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
-	/* Region 2 - OCRAM. Noncacheable. */
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(ocram), okay)
-	MPU_REGION_ENTRY("OCRAM",
-					DT_REG_ADDR(DT_NODELABEL(ocram)),
-					REGION_RAM_NOCACHE_ATTR(REGION_256K)),
-#endif
 
 #ifndef CONFIG_NXP_IMX_EXTERNAL_SDRAM
 	/*
-	 * Region 3 - mark SDRAM0 as device type memory to prevent core
+	 * Region 2 - mark SDRAM0 as device type memory to prevent core
 	 * from executing speculative prefetches against this region when
 	 * no SDRAM is present.
 	 */

soc/arm/nxp_imx/rt/sections.ld

@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2022 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/linker/linker-tool.h>
-
-#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
-
-#if (DT_REG_SIZE(DT_NODELABEL(ocram)) > 0) && !IS_CHOSEN_SRAM(ocram)
-GROUP_START(OCRAM)
-	__ocram_start = .;
-	SECTION_PROLOGUE(.ocram_bss,(NOLOAD),SUBALIGN(4))
-	{
-		__ocram_bss_start = .;
-		*(.ocram_bss)
-		*(".ocram_bss.*")
-		__ocram_bss_end = .;
-		__ocram_end = .;
-	} GROUP_LINK_IN(OCRAM)
-	SECTION_PROLOGUE(.ocram_noinit,(NOLOAD),SUBALIGN(4))
-	{
-		__ocram_noinit_start = .;
-		*(.ocram_noinit)
-		*(".ocram_noinit.*")
-		__ocram_noinit_end = .;
-	} GROUP_LINK_IN(OCRAM)
-	SECTION_PROLOGUE(.ocram_data,,SUBALIGN(4))
-	{
-		__ocram_data_start = .;
-		*(.ocram_data)
-		*(".ocram_data.*")
-		__ocram_data_end = .;
-	} GROUP_LINK_IN(OCRAM AT> ROMABLE_REGION)
-	__ocram_end = .;
-
-	__ocram_data_load_start = LOADADDR(.ocram_data);
-#endif

soc/arm/nxp_imx/rt/soc.h

@@ -26,19 +26,6 @@ void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
 
 #endif
 
-#if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \
-	CONFIG_OCRAM_NOCACHE
-/* OCRAM addresses will be defined by linker */
-extern char __ocram_start;
-extern char __ocram_bss_start;
-extern char __ocram_bss_end;
-extern char __ocram_noinit_start;
-extern char __ocram_noinit_end;
-extern char __ocram_data_start;
-extern char __ocram_data_end;
-extern char __ocram_end;
-extern char __ocram_data_load_start;
-#endif
 #if CONFIG_MIPI_DSI
 void imxrt_pre_init_display_interface(void);
 

soc/arm/nxp_imx/rt/soc_rt10xx.c

@@ -332,14 +332,6 @@ static int imxrt_init(void)
 #ifdef CONFIG_PLATFORM_SPECIFIC_INIT
 void z_arm_platform_init(void)
 {
-#if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \
-	CONFIG_OCRAM_NOCACHE
-	/* Copy data from flash to OCRAM */
-	memcpy(&__ocram_data_start, &__ocram_data_load_start,
-		(&__ocram_data_end - &__ocram_data_start));
-	/* Zero BSS region */
-	memset(&__ocram_bss_start, 0, (&__ocram_bss_end - &__ocram_bss_start));
-#endif
 	/* Call CMSIS SystemInit */
 	SystemInit();
 }

soc/arm/nxp_imx/rt/soc_rt11xx.c

@@ -682,14 +682,6 @@ static int imxrt_init(void)
 #ifdef CONFIG_PLATFORM_SPECIFIC_INIT
 void z_arm_platform_init(void)
 {
-#if (DT_DEP_ORD(DT_NODELABEL(ocram)) != DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) && \
-	CONFIG_OCRAM_NOCACHE
-	/* Copy data from flash to OCRAM */
-	memcpy(&__ocram_data_start, &__ocram_data_load_start,
-		(&__ocram_data_end - &__ocram_data_start));
-	/* Zero BSS region */
-	memset(&__ocram_bss_start, 0, (&__ocram_bss_end - &__ocram_bss_start));
-#endif
 	SystemInit();
 }
 #endif