c3dfc2220a
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve using devicetree linker regions, and there is no point in having a specific Kconfig for one memory region on the RT series like this. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
39 lines
1,002 B
C
39 lines
1,002 B
C
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SDRAM_BASE_ADDR 0x80000000
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#include <zephyr/devicetree.h>
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#include <zephyr/devicetree/memory-attr.h>
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#include "../../common/cortex_m/arm_mpu_mem_cfg.h"
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static const struct arm_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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/* Region 1 */
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MPU_REGION_ENTRY("SRAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_SIZE)),
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#ifndef CONFIG_NXP_IMX_EXTERNAL_SDRAM
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/*
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* Region 2 - mark SDRAM0 as device type memory to prevent core
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* from executing speculative prefetches against this region when
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* no SDRAM is present.
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*/
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MPU_REGION_ENTRY("SDRAM0", SDRAM_BASE_ADDR, REGION_IO_ATTR(REGION_512M)),
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#endif
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/* DT-defined regions */
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DT_MEMORY_ATTR_APPLY(ARM_MPU_REGION_INIT)
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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