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soc: intel_s1000: use EXCSAVE7 for CPU pointer

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EXCSAVE2 is used for level 2 exception save location.
Since we are using level 2 interrupts, use EXCSAVE7
instead as level 7 interrupts are not being used
by the SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2019-02-21 15:05:30 -08:00 • committed by Anas Nashif
commit ad2ee13c27
1 changed files with 2 additions and 2 deletions
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4
soc/xtensa/intel_s1000/Kconfig.defconfig
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@ -12,9 +12,9 @@ config IRQ_OFFLOAD_INTNUM
default 0
# S1000 does not have MISC0.
# Since EXCSAVE2 is unused by Zephyr, use it instead.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
default "EXCSAVE7"
config SPI_DW_FIFO_DEPTH
default 32