From ad2ee13c2795aa92a007f5fa8629656aa8a6c06a Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Thu, 21 Feb 2019 15:05:30 -0800 Subject: [PATCH] soc: intel_s1000: use EXCSAVE7 for CPU pointer EXCSAVE2 is used for level 2 exception save location. Since we are using level 2 interrupts, use EXCSAVE7 instead as level 7 interrupts are not being used by the SoC. Signed-off-by: Daniel Leung --- soc/xtensa/intel_s1000/Kconfig.defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/soc/xtensa/intel_s1000/Kconfig.defconfig b/soc/xtensa/intel_s1000/Kconfig.defconfig index 90304fd3f3e..e0e813aa0af 100644 --- a/soc/xtensa/intel_s1000/Kconfig.defconfig +++ b/soc/xtensa/intel_s1000/Kconfig.defconfig @@ -12,9 +12,9 @@ config IRQ_OFFLOAD_INTNUM default 0 # S1000 does not have MISC0. -# Since EXCSAVE2 is unused by Zephyr, use it instead. +# Since EXCSAVE7 is unused by Zephyr, use it instead. config XTENSA_KERNEL_CPU_PTR_SR - default "EXCSAVE2" + default "EXCSAVE7" config SPI_DW_FIFO_DEPTH default 32