michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately.

Browse source 
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.

This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).

When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2019-10-31 22:40:06 +09:00 • committed by Johan Hedberg
commit 8a29685a25
3 changed files with 35 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts
View file

@ -6,7 +6,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include <arm/xilinx/zynqmp.dtsi> #include <arm/xilinx/zynqmp_rpu.dtsi>
/ { / {
model = "QEMU Cortex-R5"; model = "QEMU Cortex-R5";

23
dts/arm/xilinx/zynqmp.dtsi
View file

@ -9,30 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
/ { / {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r4";
reg = <0>;
};
};
soc { soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic";
reg = <0xf9010000 0x1000>,
<0xf9020000 0x100>;
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";
status = "okay";
};
flash0: flash@c0000000 { flash0: flash@c0000000 {
compatible = "soc-nv-flash"; compatible = "soc-nv-flash";
reg = <0xc0000000 DT_SIZE_K(64)>; reg = <0xc0000000 DT_SIZE_K(64)>;

34
dts/arm/xilinx/zynqmp_rpu.dtsi Normal file
View file

@ -0,0 +1,34 @@
/*
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/xilinx/zynqmp.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r4";
reg = <0>;
};
};
soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic";
reg = <0xf9010000 0x1000>,
<0xf9020000 0x100>;
interrupt-controller;
#interrupt-cells = <4>;
label = "GIC";
status = "okay";
};
};
};