diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts b/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts
index 8deeab3ba3b..2ccde5e7e05 100644
--- a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts
+++ b/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts
@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <arm/xilinx/zynqmp.dtsi>
+#include <arm/xilinx/zynqmp_rpu.dtsi>
 
 / {
 	model = "QEMU Cortex-R5";
diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi
index 453b589e876..fbfe2b775a2 100644
--- a/dts/arm/xilinx/zynqmp.dtsi
+++ b/dts/arm/xilinx/zynqmp.dtsi
@@ -9,30 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-r4";
-			reg = <0>;
-		};
-	};
-
 	soc {
-		interrupt-parent = <&gic>;
-
-		gic: interrupt-controller@f9010000  {
-			compatible = "arm,gic";
-			reg = <0xf9010000 0x1000>,
-					<0xf9020000 0x100>;
-			interrupt-controller;
-			#interrupt-cells = <4>;
-			label = "GIC";
-			status = "okay";
-		};
-
 		flash0: flash@c0000000 {
 			compatible = "soc-nv-flash";
 			reg = <0xc0000000 DT_SIZE_K(64)>;
diff --git a/dts/arm/xilinx/zynqmp_rpu.dtsi b/dts/arm/xilinx/zynqmp_rpu.dtsi
new file mode 100644
index 00000000000..7fa3ad31bc4
--- /dev/null
+++ b/dts/arm/xilinx/zynqmp_rpu.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/xilinx/zynqmp.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r4";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@f9010000 {
+			compatible = "arm,gic";
+			reg = <0xf9010000 0x1000>,
+					<0xf9020000 0x100>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			label = "GIC";
+			status = "okay";
+		};
+	};
+};