From 8a29685a25e6693f0276a7fc54c35793f45f919f Mon Sep 17 00:00:00 2001 From: Stephanos Ioannidis Date: Thu, 31 Oct 2019 22:40:06 +0900 Subject: [PATCH] dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately. ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis --- boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts | 2 +- dts/arm/xilinx/zynqmp.dtsi | 23 ------------- dts/arm/xilinx/zynqmp_rpu.dtsi | 34 ++++++++++++++++++++ 3 files changed, 35 insertions(+), 24 deletions(-) create mode 100644 dts/arm/xilinx/zynqmp_rpu.dtsi diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts b/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts index 8deeab3ba3b..2ccde5e7e05 100644 --- a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts +++ b/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts @@ -6,7 +6,7 @@ */ /dts-v1/; -#include +#include / { model = "QEMU Cortex-R5"; diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi index 453b589e876..fbfe2b775a2 100644 --- a/dts/arm/xilinx/zynqmp.dtsi +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -9,30 +9,7 @@ #include / { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-r4"; - reg = <0>; - }; - }; - soc { - interrupt-parent = <&gic>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic"; - reg = <0xf9010000 0x1000>, - <0xf9020000 0x100>; - interrupt-controller; - #interrupt-cells = <4>; - label = "GIC"; - status = "okay"; - }; - flash0: flash@c0000000 { compatible = "soc-nv-flash"; reg = <0xc0000000 DT_SIZE_K(64)>; diff --git a/dts/arm/xilinx/zynqmp_rpu.dtsi b/dts/arm/xilinx/zynqmp_rpu.dtsi new file mode 100644 index 00000000000..7fa3ad31bc4 --- /dev/null +++ b/dts/arm/xilinx/zynqmp_rpu.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2019 Stephanos Ioannidis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r4"; + reg = <0>; + }; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@f9010000 { + compatible = "arm,gic"; + reg = <0xf9010000 0x1000>, + <0xf9020000 0x100>; + interrupt-controller; + #interrupt-cells = <4>; + label = "GIC"; + status = "okay"; + }; + }; +};