7db0fedcfe
Support custom RISC-V CSR context switch for Andes V5 CPUs. Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be saved for thread and ISR context, so adding these CSRs into the RISC-V SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE). Signed-off-by: Jim Shu <cwshu@andestech.com>
66 lines
1.2 KiB
Text
66 lines
1.2 KiB
Text
# Copyright (c) 2021 Andes Technology Corporation
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Andes V5 SoC Selection"
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depends on SOC_SERIES_RISCV_ANDES_V5
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config SOC_RISCV_ANDES_AE350
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bool "Andes AE350 SoC implementation"
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select ATOMIC_OPERATIONS_BUILTIN
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endchoice
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if SOC_SERIES_RISCV_ANDES_V5
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choice
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prompt "Base CPU ISA options"
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default RV32I_CPU
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config RV32I_CPU
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bool "RISCV32 CPU ISA"
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config RV64I_CPU
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bool "RISCV64 CPU ISA"
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select 64BIT
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endchoice
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choice
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prompt "FPU options"
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default NO_FPU
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config NO_FPU
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bool "No FPU"
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config SINGLE_PRECISION_FPU
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bool "Single precision FPU"
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select CPU_HAS_FPU
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config DOUBLE_PRECISION_FPU
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bool "Double precision FPU"
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select CPU_HAS_FPU_DOUBLE_PRECISION
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endchoice
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config CACHE_ENABLE
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bool "Enable cache"
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default n
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config SOC_ANDES_V5_HWDSP
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bool "Enable AndeStar V5 DSP ISA"
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select RISCV_SOC_CONTEXT_SAVE
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depends on !RISCV_GENERIC_TOOLCHAIN
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help
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This option enables the AndeStar v5 hardware DSP, in order to
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support using the DSP instructions.
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config SOC_ANDES_V5_PFT
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bool "Enable Andes V5 PowerBrake extension"
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default y
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select RISCV_SOC_CONTEXT_SAVE
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help
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The PowerBrake extension throttles performance by reducing instruction
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executing rate.
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endif # SOC_SERIES_RISCV_ANDES_V5
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