xtensa: remove legacy arch implementation

We re-wrote the xtensa arch code, but never got around
to purging the old implementation.

Removed those boards which hadn't been moved to the new
arch code. These were all xt-sim simulator targets and not
real hardware.

Fixes: #18138

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-08-13 14:02:29 -07:00 committed by Anas Nashif
commit 6fd6b7e50a
67 changed files with 5 additions and 8943 deletions

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@ -48,6 +48,8 @@ config RISCV
config XTENSA config XTENSA
bool "Xtensa architecture" bool "Xtensa architecture"
select HAS_DTS select HAS_DTS
select USE_SWITCH
select USE_SWITCH_SUPPORTED
config ARCH_POSIX config ARCH_POSIX
bool "POSIX (native) architecture" bool "POSIX (native) architecture"

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@ -31,17 +31,6 @@ config XTENSA_OMIT_HIGH_INTERRUPTS
code. Default is "n" for legacy compatibility. Consider code. Default is "n" for legacy compatibility. Consider
changing to "y" in the future. changing to "y" in the future.
config XTENSA_ASM2
bool "New-style Xtensa context switch & interrupt layer"
select USE_SWITCH
select USE_SWITCH_SUPPORTED
help
This selects a new implementation of context switching and
interrupt handling. Advantages are a much lower interrupt
overhead and smaller code size, and this scheme is required
for SMP. Assumes/requires hardware that implements the
register window extension, however.
endmenu endmenu
config ARCH config ARCH

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@ -5,24 +5,10 @@ zephyr_sources(
cpu_idle.c cpu_idle.c
fatal.c fatal.c
window_vectors.S window_vectors.S
)
zephyr_sources_ifdef(CONFIG_XTENSA_ASM2
xtensa-asm2-util.S xtensa-asm2-util.S
xtensa-asm2.c xtensa-asm2.c
) )
zephyr_sources_ifndef(CONFIG_XTENSA_ASM2
xtensa_intr.c
irq_manage.c
swap.S
thread.c
xtensa_context.S
xtensa_intr_asm.S
xtensa_vectors.S
xt_zephyr.S
)
zephyr_sources_ifndef(CONFIG_ATOMIC_OPERATIONS_C atomic.S) zephyr_sources_ifndef(CONFIG_ATOMIC_OPERATIONS_C atomic.S)
zephyr_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 zephyr_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1
crt1.S crt1.S

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@ -1,51 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/types.h>
#include <stdio.h>
#include <xtensa_api.h>
#include <kernel_arch_data.h>
#include <sys/__assert.h>
/*
* @internal
*
* @brief Set an interrupt's priority
*
* The priority is verified if ASSERT_ON is enabled.
*
* The priority is verified if ASSERT_ON is enabled. The maximum number of
* priority levels is a little complex, as there are some hardware priority
* levels which are reserved: three for various types of exceptions, and
* possibly one additional to support zero latency interrupts.
*
* Valid values are from 1 to 6. Interrupts of priority 1 are not masked when
* interrupts are locked system-wide, so care must be taken when using them.
* ISR installed with priority 0 interrupts cannot make kernel calls.
*
* @return N/A
*/
void z_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
{
__ASSERT(prio < XCHAL_EXCM_LEVEL + 1,
"invalid priority %d! values must be less than %d\n",
prio, XCHAL_EXCM_LEVEL + 1);
/* TODO: Write code to set priority if this is ever possible on
* Xtensa
*/
}
#ifdef CONFIG_DYNAMIC_INTERRUPTS
int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
void (*routine)(void *parameter), void *parameter,
u32_t flags)
{
ARG_UNUSED(flags);
ARG_UNUSED(priority);
z_isr_install(irq, routine, parameter);
return irq;
}
#endif /* CONFIG_DYNAMIC_INTERRUPTS */

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@ -1,93 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief kernel swapper code for Xtensa
*
* This module implements the __swap() routine for the Xtensa architecture.
*/
#include <xtensa_context.h>
#include <kernel_arch_data.h>
#include <offsets_short.h>
.extern _kernel
/* unsigned int __swap (unsigned int basepri); */
.globl __swap
.type __swap,@function
.align 4
__swap:
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, -XT_SOL_FRMSZ
#else
entry sp, XT_SOL_FRMSZ
#endif
s32i a0, sp, XT_SOL_pc
s32i a2, sp, XT_SOL_ps
#ifdef __XTENSA_CALL0_ABI__
s32i a12, sp, XT_SOL_a12 /* save callee-saved registers */
s32i a13, sp, XT_SOL_a13
s32i a14, sp, XT_SOL_a14
s32i a15, sp, XT_SOL_a15
#else
/* Spill register windows. Calling xthal_window_spill() causes extra
* spills and reloads, so we will set things up to call the _nw version
* instead to save cycles.
*/
/* spills a4-a7 if needed */
movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK)
and a2, a2, a6 /* clear WOE, INTLEVEL */
addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */
wsr a2, PS
rsync
call0 xthal_window_spill_nw
l32i a2, sp, XT_SOL_ps /* restore PS */
addi a2, a2, XCHAL_EXCM_LEVEL
wsr a2, PS
#endif
#if XCHAL_CP_NUM > 0
/* Save coprocessor callee-saved state (if any). At this point CPENABLE
* should still reflect which CPs were in use (enabled).
*/
call0 _xt_coproc_savecs
#endif
movi a2, _kernel
movi a3, 0
l32i a4, a2, KERNEL_OFFSET(current) /* a4 := _kernel->current */
s32i a3, sp, XT_SOL_exit /* 0 to flag as solicited frame */
s32i sp, a4, THREAD_OFFSET(sp) /* current->arch.topOfStack := sp */
/*
* Set __swap()'s default return code to -EAGAIN. This eliminates the
* need for the timeout code to set it itself.
*/
movi a3, -11 /* a3 := -EAGAIN. TODO: Use a macro here insted of 11 */
s32i a3, a4, THREAD_OFFSET(retval) /* current->arch.retval := -EAGAIN */
#if XCHAL_CP_NUM > 0
/* Clear CPENABLE, also in task's co-processor state save area. */
movi a3, 0
/* a4 = _kernel->current */
wsr a3, CPENABLE
s16i a3, a4, THREAD_OFFSET(cpEnable) /* clear saved cpenable */
#endif
#ifdef CONFIG_TRACING
/* Register the context switch */
#ifdef __XTENSA_CALL0_ABI__
call0 z_sys_trace_thread_switched_in
#else
call4 z_sys_trace_thread_switched_in
#endif
#endif
/* _thread := _kernel.ready_q.cache */
l32i a3, a2, KERNEL_OFFSET(ready_q_cache)
/*
* Swap threads if any is to be swapped in.
*/
call0 _zxt_dispatch /* (_kernel@a2, _thread@a3) */
/* Never reaches here. */

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@ -1,123 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef CONFIG_DEBUG
#include <sys/printk.h>
#endif
#include <kernel_structs.h>
#include <wait_q.h>
#include <xtensa_config.h>
#include <kernel_internal.h>
extern void z_xt_user_exit(void);
/*
* @brief Initialize a new thread
*
* Any coprocessor context data is put at the lower address of the stack. An
* initial context, to be "restored" by __return_from_coop(), is put at
* the other end of the stack, and thus reusable by the stack when not
* needed anymore.
*
* The initial context is a basic stack frame that contains arguments for
* z_thread_entry() return address, that points at z_thread_entry()
* and status register.
*
* <options> is currently unused.
*
* @param thread pointer to k_thread memory
* @param pStackmem the pointer to aligned stack memory
* @param stackSize the stack size in bytes
* @param pEntry thread entry point routine
* @param p1 first param to entry point
* @param p2 second param to entry point
* @param p3 third param to entry point
* @param priority thread priority
* @param options is unused (saved for future expansion)
*
* @return N/A
*/
void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
size_t stackSize, k_thread_entry_t pEntry,
void *p1, void *p2, void *p3,
int priority, unsigned int options)
{
char *pStack = Z_THREAD_STACK_BUFFER(stack);
/* Align stack end to maximum alignment requirement. */
char *stackEnd = (char *)ROUND_DOWN(pStack + stackSize, 16);
#if XCHAL_CP_NUM > 0
u32_t *cpSA;
char *cpStack;
#endif
z_new_thread_init(thread, pStack, stackSize, priority, options);
#ifdef CONFIG_DEBUG
printk("\nstackPtr = %p, stackSize = %d\n", pStack, stackSize);
printk("stackEnd = %p\n", stackEnd);
#endif
#if XCHAL_CP_NUM > 0
/* Ensure CP state descriptor is correctly initialized */
cpStack = thread->arch.preempCoprocReg.cpStack; /* short hand alias */
/* Set to zero to avoid bad surprises */
(void)memset(cpStack, 0, XT_CP_ASA);
/* Coprocessor's stack is allocated just after the k_thread */
cpSA = (u32_t *)(thread->arch.preempCoprocReg.cpStack + XT_CP_ASA);
/* Coprocessor's save area alignment is at leat 16 bytes */
*cpSA = ROUND_UP(cpSA + 1,
(XCHAL_TOTAL_SA_ALIGN < 16 ? 16 : XCHAL_TOTAL_SA_ALIGN));
#ifdef CONFIG_DEBUG
printk("cpStack = %p\n", thread->arch.preempCoprocReg.cpStack);
printk("cpAsa = %p\n",
*(void **)(thread->arch.preempCoprocReg.cpStack + XT_CP_ASA));
#endif
#endif
/* Thread's first frame alignment is granted as both operands are
* aligned
*/
XtExcFrame *pInitCtx =
(XtExcFrame *)(stackEnd - (XT_XTRA_SIZE - XT_CP_SIZE));
#ifdef CONFIG_DEBUG
printk("pInitCtx = %p\n", pInitCtx);
#endif
/* Explicitly initialize certain saved registers */
/* task entrypoint */
pInitCtx->pc = (u32_t)z_thread_entry;
/* physical top of stack frame */
pInitCtx->a1 = (u32_t)pInitCtx + XT_STK_FRMSZ;
/* user exception exit dispatcher */
pInitCtx->exit = (u32_t)z_xt_user_exit;
/* Set initial PS to int level 0, EXCM disabled, user mode.
* Also set entry point argument arg.
*/
#ifdef __XTENSA_CALL0_ABI__
pInitCtx->a2 = (u32_t)pEntry;
pInitCtx->a3 = (u32_t)p1;
pInitCtx->a4 = (u32_t)p2;
pInitCtx->a5 = (u32_t)p3;
pInitCtx->ps = PS_UM | PS_EXCM;
#else
/* For windowed ABI set also WOE and CALLINC
* (pretend task is 'call4')
*/
pInitCtx->a6 = (u32_t)pEntry;
pInitCtx->a7 = (u32_t)p1;
pInitCtx->a8 = (u32_t)p2;
pInitCtx->a9 = (u32_t)p3;
pInitCtx->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
#endif
thread->callee_saved.topOfStack = pInitCtx;
thread->arch.flags = 0;
/* initial values in all other registers/k_thread entries are
* irrelevant
*/
}

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@ -1,386 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa_context.h>
#include <xtensa_timer.h>
#include <offsets_short.h>
#include <kernel_structs.h>
.extern _interrupt_stack
.extern _kernel
#ifdef CONFIG_SYS_CLOCK_EXISTS
.extern timer_int_handler
#endif
.set _interrupt_stack_top, _interrupt_stack + CONFIG_ISR_STACK_SIZE
/*
* _zxt_dispatch(_kernel_t *_kernel, _thread_t *_thread)
* At this point, the a2 register contains the '&_kernel' and the
* thread to be swapped in (&_thread) is in a3.
*/
.text
.globl _zxt_dispatch
.type _zxt_dispatch,@function
.align 4
_zxt_dispatch:
/* Updated current thread: _kernel.current := _kernel.ready_q.cache */
s32i a3, a2, KERNEL_OFFSET(current) /* _kernel.current := _thread */
l32i sp, a3, THREAD_OFFSET(sp) /* sp := _thread->topOfStack; */
/* Determine the type of stack frame. */
l32i a2, sp, XT_STK_exit /* exit dispatcher or solicited flag */
bnez a2, .L_frxt_dispatch_stk
.L_frxt_dispatch_sol:
/* Solicited stack frame. Restore retval from z_swap */
l32i a2, a3, THREAD_OFFSET(retval)
l32i a3, sp, XT_SOL_ps
#ifdef __XTENSA_CALL0_ABI__
l32i a12, sp, XT_SOL_a12
l32i a13, sp, XT_SOL_a13
l32i a14, sp, XT_SOL_a14
l32i a15, sp, XT_SOL_a15
#endif
l32i a0, sp, XT_SOL_pc
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE is complete (should be, it was cleared on
* entry).
*/
rsync
#endif
/* As soons as PS is restored, interrupts can happen. No need to sync
* PS.
*/
wsr a3, PS
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, XT_SOL_FRMSZ
ret
#else
retw
#endif
.L_frxt_dispatch_stk:
#if XCHAL_CP_NUM > 0
/* Restore CPENABLE from task's co-processor save area. */
l16ui a3, a3, THREAD_OFFSET(cpEnable) /* a3 := cp_state->cpenable */
wsr a3, CPENABLE
#endif
#ifdef CONFIG_STACK_SENTINEL
#ifdef __XTENSA_CALL0_ABI__
call0 z_check_stack_sentinel
#else
call4 z_check_stack_sentinel
#endif
#endif
/*
* Interrupt stack frame.
* Restore full context and return to exit dispatcher.
*/
call0 _xt_context_restore
/* In Call0 ABI, restore callee-saved regs (A12, A13 already
* restored).
*/
#ifdef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_a14
l32i a15, sp, XT_STK_a15
#endif
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE has completed. */
rsync
#endif
/*
* Must return via the exit dispatcher corresponding to the entrypoint
* from which this was called. Interruptee's A0, A1, PS, PC are
* restored and the interrupt stack frame is deallocated in the exit
* dispatcher.
*/
l32i a0, sp, XT_STK_exit
ret
/*
* _zxt_int_enter
* void _zxt_int_enter(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
* freeRTOS. Saves the rest of the interrupt context (not already saved).
* May only be called from assembly code by the 'call0' instruction, with
* interrupts disabled.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*/
.globl _zxt_int_enter
.type _zxt_int_enter,@function
.align 4
_zxt_int_enter:
/* Save a12-13 in the stack frame as required by _xt_context_save. */
s32i a12, a1, XT_STK_a12
s32i a13, a1, XT_STK_a13
/* Save return address in a safe place (free a0). */
mov a12, a0
/* Save the rest of the interrupted context (preserves A12-13). */
call0 _xt_context_save
/*
* Save interrupted task's SP in TCB only if not nesting. Manage
* nesting directly rather than call the generic IntEnter() (in
* windowed ABI we can't call a C function here anyway because PS.EXCM
* is still set).
*/
movi a2, _kernel /* a2 := _kernel */
l32i a3, a2, KERNEL_OFFSET(nested) /* a3 := _kernel->nested */
addi a3, a3, 1 /* increment nesting count */
s32i a3, a2, KERNEL_OFFSET(nested) /* save nesting count */
bnei a3, 1, .Lnested /* !=0 before incr, so nested */
l32i a3, a2, KERNEL_OFFSET(current)/* a3 := _kernel->current */
s32i a1, a3, THREAD_OFFSET(sp) /* save SP to Current top of stack */
movi a1, _interrupt_stack_top /* a1 = top of intr stack */
.Lnested:
1:
mov a0, a12 /* restore return addr and return */
ret
/*
* _zxt_int_exit
* void _zxt_int_exit(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
* Zephyr. If required, calls vPortYieldFromInt() to perform task context
* switching, restore the (possibly) new task's context, and return to the exit
* dispatcher saved in the task's stack frame at XT_STK_EXIT. May only be
* called from assembly code by the 'call0' instruction. Does not return to
* caller. See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*/
.globl _zxt_int_exit
.type _zxt_int_exit,@function
.align 4
_zxt_int_exit:
rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */
movi a2, _kernel
l32i a3, a2, KERNEL_OFFSET(nested) /* _kernel->nested */
addi a3, a3, -1 /* decrement nesting count */
s32i a3, a2, KERNEL_OFFSET(nested) /* save nesting count */
bnez a3, .Lnesting /* !=0 after decr so still nested */
/*
* When using call0 ABI callee-saved registers a12-15 need to be saved
* before enabling preemption. They were already saved by
* _zxt_int_enter().
*/
#ifdef __XTENSA_CALL0_ABI__
s32i a14, a1, XT_STK_a14
s32i a15, a1, XT_STK_a15
#endif
#if XCHAL_CP_NUM > 0
l32i a3, a2, KERNEL_OFFSET(current) /* _thread := _kernel->current */
rsr a5, CPENABLE
s16i a5, a3, THREAD_OFFSET(cpEnable) /* cp_state->cpenable = CPENABLE */
movi a3, 0
wsr a3, CPENABLE /* disable all co-processors */
#endif
l32i a3, a2, KERNEL_OFFSET(current) /* _thread := _kernel.current */
/* _thread := _kernel.ready_q.cache */
l32i a3, a2, KERNEL_OFFSET(ready_q_cache)
.noReschedule:
/*
* Swap threads if any is to be swapped in.
*/
call0 _zxt_dispatch /* (_kernel@a2, _thread@a3) */
/* Never returns here. */
.Lnesting:
/*
* We come here only if there was no context switch, that is if this
* is a nested interrupt, or the interrupted task was not preempted.
* In either case there's no need to load the SP.
*/
/* Restore full context from interrupt stack frame */
call0 _xt_context_restore
/*
* Must return via the exit dispatcher corresponding to the entrypoint
* from which this was called. Interruptee's A0, A1, PS, PC are
* restored and the interrupt stack frame is deallocated in the exit
* dispatcher.
*/
l32i a0, sp, XT_STK_exit
ret
/*
* _zxt_timer_int
* void _zxt_timer_int(void)
*
* Implements Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function. Called
* every timer interrupt. Manages the tick timer and calls
* xPortSysTickHandler() every tick. See the detailed description of the
* XT_RTOS_ENTER macro in xtensa_rtos.h. Callable from C. Implemented in
* assembly code for performance.
*
*/
.globl _zxt_timer_int
.type _zxt_timer_int,@function
.align 4
_zxt_timer_int:
/*
* Xtensa timers work by comparing a cycle counter with a preset value.
* Once the match occurs an interrupt is generated, and the handler has
* to set a new cycle count into the comparator. To avoid clock drift
* due to interrupt latency, the new cycle count is computed from the
* old, not the time the interrupt was serviced. However if a timer
* interrupt is ever serviced more than one tick late, it is necessary
* to process multiple ticks until the new cycle count is in the
* future, otherwise the next timer interrupt would not occur until
* after the cycle counter had wrapped (2^32 cycles later).
*
* do {
* ticks++;
* old_ccompare = read_ccompare_i();
* write_ccompare_i( old_ccompare + divisor );
* service one tick;
* diff = read_ccount() - old_ccompare;
* } while ( diff > divisor );
*/
ENTRY(16)
.L_xt_timer_int_catchup:
#ifdef CONFIG_SYS_CLOCK_EXISTS
#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0)
/* Update the timer comparator for the next tick. */
#ifdef XT_CLOCK_FREQ
movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
#else
movi a3, _xt_tick_divisor
l32i a2, a3, 0 /* a2 = comparator increment */
#endif
rsr a3, XT_CCOMPARE /* a3 = old comparator value */
add a4, a3, a2 /* a4 = new comparator value */
wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
esync
#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */
#ifdef __XTENSA_CALL0_ABI__
/* Preserve a2 and a3 across C calls. */
s32i a2, sp, 4
s32i a3, sp, 8
/* TODO: movi a2, _xt_interrupt_table */
movi a3, timer_int_handler
/* TODO: l32i a2, a2, 0 */
callx0 a3
/* Restore a2 and a3. */
l32i a2, sp, 4
l32i a3, sp, 8
#else
/* TODO: movi a6, _xt_interrupt_table */
movi a7, timer_int_handler
/* TODO: l32i a6, a6, 0 */
callx4 a7
#endif
#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0)
/* Check if we need to process more ticks to catch up. */
esync /* ensure comparator update complete */
rsr a4, CCOUNT /* a4 = cycle count */
sub a4, a4, a3 /* diff = ccount - old comparator */
blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */
#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */
#endif
RET(16)
/*
* _zxt_tick_timer_init
* void _zxt_tick_timer_init(void)
*
* Initialize timer and timer interrupt handler (z_xt_tick_divisor_init() has
* already been been called).
* Callable from C (obeys ABI conventions on entry).
*
*/
.globl _zxt_tick_timer_init
.type _zxt_tick_timer_init,@function
.align 4
_zxt_tick_timer_init:
ENTRY(48)
#ifdef CONFIG_SYS_CLOCK_EXISTS
#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0)
/* Set up the periodic tick timer (assume enough time to complete
* init).
*/
#ifdef XT_CLOCK_FREQ
movi a3, XT_TICK_DIVISOR
#else
movi a2, _xt_tick_divisor
l32i a3, a2, 0
#endif
rsr a2, CCOUNT /* current cycle count */
add a2, a2, a3 /* time of first timer interrupt */
wsr a2, XT_CCOMPARE /* set the comparator */
/*
Enable the timer interrupt at the device level. Don't write directly
to the INTENABLE register because it may be virtualized.
*/
#ifdef __XTENSA_CALL0_ABI__
movi a2, XT_TIMER_INTEN
call0 z_xt_ints_on
#else
movi a6, XT_TIMER_INTEN
call4 z_xt_ints_on
#endif
#endif
#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */
RET(48)
/*
* _zxt_task_coproc_state
* void _zxt_task_coproc_state(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function.
*
* May only be called when a task is running, not within an interrupt handler
* (returns 0 in that case).
* May only be called from assembly code by the 'call0' instruction.
* Does NOT obey ABI conventions.
* Returns in A15 a pointer to the base of the co-processor state save area
* for the current task.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
*/
#if XCHAL_CP_NUM > 0
.globl _zxt_task_coproc_state
.type _zxt_task_coproc_state,@function
.align 4
_zxt_task_coproc_state:
movi a2, _kernel
l32i a15, a2, KERNEL_OFFSET(nested)
bnez a15, 1f
l32i a2, a2, KERNEL_OFFSET(current)
beqz a2, 1f
addi a15, a2, THREAD_OFFSET(cpStack)
ret
1: movi a15, 0
2: ret
#endif /* XCHAL_CP_NUM > 0 */

View file

@ -228,8 +228,6 @@ xtensa_switch:
_switch_restore_pc: _switch_restore_pc:
retw retw
#ifdef CONFIG_XTENSA_ASM2
/* Define our entry handler to load the struct kernel_t from the /* Define our entry handler to load the struct kernel_t from the
* MISC0 special register, and to find the nest and irq_stack values * MISC0 special register, and to find the nest and irq_stack values
* at the precomputed offsets. * at the precomputed offsets.
@ -320,5 +318,3 @@ _DoubleExceptionVector:
j 1b j 1b
.popsection .popsection
#endif #endif
#endif /* CONFIG_XTENSA_ASM2 */

View file

@ -53,11 +53,6 @@ void *xtensa_init_stack(int *stack_top,
return &bsa[-9]; return &bsa[-9];
} }
/* This is a kernel hook, just a wrapper around other APIs. Build
* only if we're using asm2 as the core OS interface and not just as
* utilities/testables.
*/
#ifdef CONFIG_XTENSA_ASM2
void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz, void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz,
k_thread_entry_t entry, void *p1, void *p2, void *p3, k_thread_entry_t entry, void *p1, void *p2, void *p3,
int prio, unsigned int opts) int prio, unsigned int opts)
@ -73,9 +68,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz,
thread->switch_handle = xtensa_init_stack((void *)top, entry, thread->switch_handle = xtensa_init_stack((void *)top, entry,
p1, p2, p3); p1, p2, p3);
} }
#endif
#ifdef CONFIG_XTENSA_ASM2
void z_irq_spurious(void *arg) void z_irq_spurious(void *arg)
{ {
int irqs, ie; int irqs, ie;
@ -88,7 +81,6 @@ void z_irq_spurious(void *arg)
(void *)irqs, (void *)ie); (void *)irqs, (void *)ie);
z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
#endif
void z_xtensa_dump_stack(const z_arch_esf_t *stack) void z_xtensa_dump_stack(const z_arch_esf_t *stack)
{ {

View file

@ -1,609 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
*
* Low-level Call0 functions for handling generic context save and restore of
* registers not specifically addressed by the interrupt vectors and handlers.
* Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
* Except for the calls to RTOS functions, this code is generic to Xtensa.
*
* Note that in Call0 ABI, interrupt handlers are expected to preserve the
* callee-save regs (A12-A15), which is always the case if the handlers are
* coded in C. However A12, A13 are made available as scratch registers for
* interrupt dispatch code, so are presumed saved anyway, and are always
* restored even in Call0 ABI. Only A14, A15 are truly handled as callee-save
* regs.
*
* Because Xtensa is a configurable architecture, this port supports all user
* generated configurations (except restrictions stated in the release notes).
* This is accomplished by conditional compilation using macros and functions
* defined in the Xtensa HAL (hardware adaptation layer) for your
* configuration. Only the processor state included in your configuration is
* saved and restored, including any processor state added by user
* configuration options or TIE.
*/
/* Warn nicely if this file gets named with a lowercase .s instead of .S: */
#define NOERROR #
NOERROR: .error "C preprocessor needed for this file: make sure its filename\
ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
#include "xtensa_rtos.h"
#ifdef XT_USE_OVLY
#include <xtensa/overlay_os_asm.h>
#endif
.text
/*
* _xt_context_save
*
* !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
*
* Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in
* the interrupt stack frame defined in xtensa_rtos.h. Its counterpart is
* _xt_context_restore (which also restores A12, A13).
*
* Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
* This function preserves A12 & A13 in order to provide the caller with 2
* scratch regs that need not be saved over the call to this function. The
* choice of which 2 regs to provide is governed by xthal_window_spill_nw and
* xthal_save_extra_nw, to avoid moving data more than necessary. Caller can
* assign regs accordingly.
*
* Entry Conditions:
* A0 = Return address in caller.
* A1 = Stack pointer of interrupted thread or handler ("interruptee").
* Original A12, A13 have already been saved in the interrupt stack frame.
* Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
* point of interruption.
* If windowed ABI, PS.EXCM = 1 (exceptions disabled).
*
* Exit conditions:
* A0 = Return address in caller.
* A1 = Stack pointer of interrupted thread or handler ("interruptee").
* A12, A13 as at entry (preserved).
* If windowed ABI, PS.EXCM = 1 (exceptions disabled).
*/
.global _xt_context_save
.type _xt_context_save,@function
.align 4
_xt_context_save:
s32i a2, sp, XT_STK_a2
s32i a3, sp, XT_STK_a3
s32i a4, sp, XT_STK_a4
s32i a5, sp, XT_STK_a5
s32i a6, sp, XT_STK_a6
s32i a7, sp, XT_STK_a7
s32i a8, sp, XT_STK_a8
s32i a9, sp, XT_STK_a9
s32i a10, sp, XT_STK_a10
s32i a11, sp, XT_STK_a11
/* Call0 ABI callee-saved regs a12-15 do not need to be saved here. a12-13
* are the caller's responsibility so it can use them as scratch. So only
* need to save a14-a15 here for Windowed ABI (not Call0).
*/
#ifndef __XTENSA_CALL0_ABI__
s32i a14, sp, XT_STK_a14
s32i a15, sp, XT_STK_a15
#endif
rsr a3, SAR
s32i a3, sp, XT_STK_sar
#if XCHAL_HAVE_LOOPS
rsr a3, LBEG
s32i a3, sp, XT_STK_lbeg
rsr a3, LEND
s32i a3, sp, XT_STK_lend
rsr a3, LCOUNT
s32i a3, sp, XT_STK_lcount
#endif
#if XT_USE_SWPRI
/* Save virtual priority mask */
movi a3, _xt_vpri_mask
l32i a3, a3, 0
s32i a3, sp, XT_STK_VPRI
#endif
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a9, a0 /* preserve ret addr */
#endif
#ifndef __XTENSA_CALL0_ABI__
/* To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
* Need to save a9,12,13 temporarily (in frame temps) and recover
* originals. Interrupts need to be disabled below XCHAL_EXCM_LEVEL and
* window overflow and underflow exceptions disabled (assured by PS.EXCM ==
* 1).
*/
s32i a12, sp, XT_STK_tmp0 /* temp. save stuff in stack frame */
s32i a13, sp, XT_STK_tmp1
s32i a9, sp, XT_STK_tmp2
/* Save the overlay state if we are supporting overlays. Since we just
* saved three registers, we can conveniently use them here. Note that as
* of now, overlays only work for windowed calling ABI.
*/
#ifdef XT_USE_OVLY
l32i a9, sp, XT_STK_PC /* recover saved PC */
_xt_overlay_get_state a9, a12, a13
s32i a9, sp, XT_STK_OVLY /* save overlay state */
#endif
l32i a12, sp, XT_STK_a12 /* recover original a9,12,13 */
l32i a13, sp, XT_STK_a13
l32i a9, sp, XT_STK_a9
addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
addi sp, sp, -XT_STK_FRMSZ
l32i a12, sp, XT_STK_tmp0 /* recover stuff from stack frame */
l32i a13, sp, XT_STK_tmp1
l32i a9, sp, XT_STK_tmp2
#endif
#if XCHAL_EXTRA_SA_SIZE > 0
/* NOTE: Normally the xthal_save_extra_nw macro only affects address
* registers a2-a5. It is theoretically possible for Xtensa processor
* designers to write TIE that causes more address registers to be
* affected, but it is generally unlikely. If that ever happens, more
* registers need to be saved/restored around this macro invocation. Here
* we assume a9,12,13 are preserved. Future Xtensa tools releases might
* limit the regs that can be affected.
*/
addi a2, sp, XT_STK_EXTRA /* where to save it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */
#endif
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a0, a9 /* retrieve ret addr */
#endif
ret
/*_xt_context_restore
*
* !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
*
* Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
* ABI, A14, A15 which are preserved by all interrupt handlers) from an
* interrupt stack frame defined in xtensa_rtos.h. Its counterpart is
* _xt_context_save (whose caller saved A12, A13).
*
* Caller is responsible to restore PC, PS, A0, A1 (SP).
*
* Entry Conditions:
* A0 = Return address in caller.
* A1 = Stack pointer of interrupted thread or handler ("interruptee").
*
* Exit conditions:
* A0 = Return address in caller.
* A1 = Stack pointer of interrupted thread or handler ("interruptee").
* Other processor state except PC, PS, A0, A1 (SP), is as at the point
* of interruption.
*/
.global _xt_context_restore
.type _xt_context_restore,@function
.align 4
_xt_context_restore:
#if XCHAL_EXTRA_SA_SIZE > 0
/* NOTE: Normally the xthal_restore_extra_nw macro only affects address
* registers a2-a5. It is theoretically possible for Xtensa processor
* designers to write TIE that causes more address registers to be
* affected, but it is generally unlikely. If that ever happens, more
* registers need to be saved/restored around this macro invocation. Here
* we only assume a13 is preserved. Future Xtensa tools releases might
* limit the regs that can be affected.
*/
mov a13, a0 /* preserve ret addr */
addi a2, sp, XT_STK_EXTRA /* where to find it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */
mov a0, a13 /* retrieve ret addr */
#endif
#if XCHAL_HAVE_LOOPS
l32i a2, sp, XT_STK_lbeg
l32i a3, sp, XT_STK_lend
wsr a2, LBEG
l32i a2, sp, XT_STK_lcount
wsr a3, LEND
wsr a2, LCOUNT
#endif
#ifdef XT_USE_OVLY
/* If we are using overlays, this is a good spot to check if we need to
* restore an overlay for the incoming task. Here we have a bunch of
* registers to spare. Note that this step is going to use a few bytes of
* storage below SP (SP-20 to SP-32) if an overlay is going to be
* restored.
*/
l32i a2, sp, XT_STK_pc /* retrieve PC */
l32i a3, sp, XT_STK_ps /* retrieve PS */
l32i a4, sp, XT_STK_ovly /* retrieve overlay state */
l32i a5, sp, XT_STK_a1 /* retrieve stack ptr */
_xt_overlay_check_map a2, a3, a4, a5, a6
s32i a2, sp, XT_STK_pc /* save updated PC */
s32i a3, sp, XT_STK_ps /* save updated PS */
#endif
#ifdef XT_USE_SWPRI
/* Restore virtual interrupt priority and interrupt enable */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */
and a4, a4, a5
wsr a4, INTENABLE /* update INTENABLE */
s32i a5, a3, 4 /* restore _xt_vpri_mask */
#endif
l32i a3, sp, XT_STK_sar
l32i a2, sp, XT_STK_a2
wsr a3, SAR
l32i a3, sp, XT_STK_a3
l32i a4, sp, XT_STK_a4
l32i a5, sp, XT_STK_a5
l32i a6, sp, XT_STK_a6
l32i a7, sp, XT_STK_a7
l32i a8, sp, XT_STK_a8
l32i a9, sp, XT_STK_a9
l32i a10, sp, XT_STK_a10
l32i a11, sp, XT_STK_a11
/*
* Call0 ABI callee-saved regs a12-15 do not need to be restored here.
* However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
* so need to be restored anyway, despite being callee-saved in Call0.
*/
l32i a12, sp, XT_STK_a12
l32i a13, sp, XT_STK_a13
#ifndef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_a14
l32i a15, sp, XT_STK_a15
#endif
ret
/* z_xt_coproc_init
*
* Initializes global co-processor management data, setting all co-processors
* to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
*
* Called during initialization of the RTOS, before any threads run.
*
* This may be called from normal Xtensa single-threaded application code which
* might use co-processors. The Xtensa run-time initialization enables all
* co-processors. They must remain enabled here, else a co-processor exception
* might occur outside of a thread, which the exception handler doesn't expect.
*
* Entry Conditions:
* Xtensa single-threaded run-time environment is in effect.
* No thread is yet running.
*
* Exit conditions:
* None.
*
* Obeys ABI conventions per prototype:
* void z_xt_coproc_init(void)
*/
#if XCHAL_CP_NUM > 0
.global z_xt_coproc_init
.type z_xt_coproc_init,@function
.align 4
z_xt_coproc_init:
ENTRY0
/* Initialize thread co-processor ownerships to 0 (unowned). */
movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */
movi a4, 0 /* a4 = 0 (unowned) */
1: s32i a4, a2, 0
addi a2, a2, 4
bltu a2, a3, 1b
RET0
#endif
/* _xt_coproc_release
*
* Releases any and all co-processors owned by a given thread. The thread is
* identified by it's co-processor state save area defined in xtensa_context.h
*
* Must be called before a thread's co-proc save area is deleted to avoid
* memory corruption when the exception handler tries to save the state.
* May be called when a thread terminates or completes but does not delete
* the co-proc save area, to avoid the exception handler having to save the
* thread's co-proc state before another thread can use it (optimization).
*
* Entry Conditions:
* A2 = Pointer to base of co-processor state save area.
*
* Exit conditions:
* None.
*
* Obeys ABI conventions per prototype:
* void _xt_coproc_release(void * coproc_sa_base)
*/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_release
.type _xt_coproc_release,@function
.align 4
_xt_coproc_release:
ENTRY0 /* a2 = base of save area */
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
movi a5, 0 /* a5 = 0 (unowned) */
rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */
1: l32i a7, a3, 0 /* a7 = owner at a3 */
bne a2, a7, 2f /* if (coproc_sa_base == owner) */
s32i a5, a3, 0 /* owner = unowned */
2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */
bltu a3, a4, 1b /* repeat until end of array */
3: wsr a6, PS /* restore interrupts */
RET0
#endif
/* _xt_coproc_savecs
*
* If there is a current thread and it has a coprocessor state save area, then
* save all callee-saved state into this area. This function is called from the
* solicited context switch handler. It calls a system-specific function to get
* the coprocessor save area base address.
*
* Entry conditions:
* - The thread being switched out is still the current thread.
* - CPENABLE state reflects which coprocessors are active.
* - Registers have been saved/spilled already.
*
* Exit conditions:
* - All necessary CP callee-saved state has been saved.
* - Registers a2-a7, a13-a15 have been trashed.
*
* Must be called from assembly code only, using CALL0.
*/
#if XCHAL_CP_NUM > 0
.extern _xt_coproc_sa_offset /* external reference */
.global _xt_coproc_savecs
.type _xt_coproc_savecs,@function
.align 4
_xt_coproc_savecs:
/* At entry, CPENABLE should be showing which CPs are enabled. */
rsr a2, CPENABLE /* a2 = which CPs are enabled */
beqz a2, .Ldone /* quick exit if none */
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone /* if none then nothing to do */
s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone:
ret
#endif
/*
* _xt_coproc_restorecs
*
* Restore any callee-saved coprocessor state for the incoming thread.
* This function is called from coprocessor exception handling, when giving
* ownership to a thread that solicited a context switch earlier. It calls a
* system-specific function to get the coprocessor save area base address.
*
* Entry conditions:
* - The incoming thread is set as the current thread.
* - CPENABLE is set up correctly for all required coprocessors.
* - a2 = mask of coprocessors to be restored.
*
* Exit conditions:
* - All necessary CP callee-saved state has been restored.
* - CPENABLE - unchanged.
* - Registers a2-a7, a13-a15 have been trashed.
*
* Must be called from assembly code only, using CALL0.
*/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_restorecs
.type _xt_coproc_restorecs,@function
.align 4
_xt_coproc_restorecs:
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone2 /* if none then nothing to do */
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
xor a3, a3, a2 /* clear the ones being restored */
s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \
select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone2:
ret
#endif

View file

@ -1,39 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Xtensa-specific interrupt and exception functions for RTOS ports.
* Also see xtensa_intr_asm.S.
*/
#include <stdlib.h>
#include <xtensa/config/core.h>
#include "xtensa_rtos.h"
#include "xtensa_api.h"
#include <kernel_structs.h>
#include <sw_isr_table.h>
#if XCHAL_HAVE_EXCEPTIONS
static void unhandled_exception_trampoline(XtExcFrame *frame)
{
FatalErrorHandler();
CODE_UNREACHABLE;
}
typedef void (*xt_exc_handler)(XtExcFrame *);
xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM] __aligned(4) = {
[0 ... (XCHAL_EXCCAUSE_NUM - 1)] = unhandled_exception_trampoline
};
#endif
#if defined(CONFIG_SW_ISR_TABLE) && defined(XCHAL_HAVE_INTERRUPTS)
void z_irq_spurious(void *arg)
{
ReservedInterruptHandler((unsigned int)arg);
CODE_UNREACHABLE;
}
#endif

View file

@ -1,118 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/******************************************************************************
Xtensa interrupt handling data and assembly routines.
Also see xtensa_intr.c and xtensa_vectors.S.
******************************************************************************/
#include <xtensa/hal.h>
#include <xtensa/config/core.h>
#include "xtensa_rtos.h"
#include "xtensa_context.h"
#if XCHAL_HAVE_INTERRUPTS
/*
-------------------------------------------------------------------------------
INTENABLE virtualization information.
-------------------------------------------------------------------------------
*/
.data
.global _xt_intdata
.align 8
_xt_intdata:
.global _xt_intenable
.type _xt_intenable,@object
.size _xt_intenable,4
.global _xt_vpri_mask
.type _xt_vpri_mask,@object
.size _xt_vpri_mask,4
_xt_intenable: .word 0 /* Virtual INTENABLE */
_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
#endif /* XCHAL_HAVE_INTERRUPTS */
/*
-------------------------------------------------------------------------------
unsigned int z_xt_ints_on ( unsigned int mask )
Enables a set of interrupts. Does not simply set INTENABLE directly, but
computes it as a function of the current virtual priority.
Can be called from interrupt handlers.
-------------------------------------------------------------------------------
*/
.text
.align 4
.global z_xt_ints_on
.type z_xt_ints_on,@function
z_xt_ints_on:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xt_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xt_intenable */
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
or a5, a3, a2 /* a5 = _xt_intenable | mask */
s32i a5, a4, 0 /* _xt_intenable |= mask */
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* Return zero */
#endif
RET0
.size z_xt_ints_on, . - z_xt_ints_on
/*
-------------------------------------------------------------------------------
unsigned int z_xt_ints_off ( unsigned int mask )
Disables a set of interrupts. Does not simply set INTENABLE directly,
but computes it as a function of the current virtual priority.
Can be called from interrupt handlers.
-------------------------------------------------------------------------------
*/
.text
.align 4
.global z_xt_ints_off
.type z_xt_ints_off,@function
z_xt_ints_off:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xt_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xt_intenable */
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
or a5, a3, a2 /* a5 = _xt_intenable | mask */
xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
s32i a5, a4, 0 /* _xt_intenable &= ~mask */
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* return zero */
#endif
RET0
.size z_xt_ints_off, . - z_xt_ints_off

File diff suppressed because it is too large Load diff

View file

@ -51,10 +51,8 @@ extern "C" {
typedef struct __esf __esf_t; typedef struct __esf __esf_t;
#ifdef CONFIG_USE_SWITCH
void xtensa_switch(void *switch_to, void **switched_from); void xtensa_switch(void *switch_to, void **switched_from);
#define z_arch_switch xtensa_switch #define z_arch_switch xtensa_switch
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }

View file

@ -44,15 +44,11 @@ extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE);
static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void) static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void)
{ {
#ifdef CONFIG_XTENSA_ASM2
void *val; void *val;
val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR); val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
return val; return val;
#else
return &_kernel.cpus[0];
#endif
} }
/** /**
@ -70,8 +66,6 @@ static ALWAYS_INLINE void kernel_arch_init(void)
_cpu_t *cpu0 = &_kernel.cpus[0]; _cpu_t *cpu0 = &_kernel.cpus[0];
cpu0->nested = 0; cpu0->nested = 0;
#if CONFIG_XTENSA_ASM2
cpu0->irq_stack = (Z_THREAD_STACK_BUFFER(_interrupt_stack) + cpu0->irq_stack = (Z_THREAD_STACK_BUFFER(_interrupt_stack) +
CONFIG_ISR_STACK_SIZE); CONFIG_ISR_STACK_SIZE);
@ -82,14 +76,6 @@ static ALWAYS_INLINE void kernel_arch_init(void)
* already is a big win. * already is a big win.
*/ */
WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0); WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0);
#endif
#if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0
/* Initialize co-processor management for threads.
* Leave CPENABLE alone.
*/
z_xt_coproc_init();
#endif
#ifdef CONFIG_INIT_STACKS #ifdef CONFIG_INIT_STACKS
memset(Z_THREAD_STACK_BUFFER(_interrupt_stack), 0xAA, memset(Z_THREAD_STACK_BUFFER(_interrupt_stack), 0xAA,
@ -97,27 +83,6 @@ static ALWAYS_INLINE void kernel_arch_init(void)
#endif #endif
} }
/**
*
* @brief Set the return value for the specified thread (inline)
*
* @param thread pointer to thread
* @param value value to set as return value
*
* The register used to store the return value from a function call invocation
* is set to <value>. It is assumed that the specified thread is pending, and
* thus the thread's context is stored in its k_thread.
*
* @return N/A
*/
#if !CONFIG_USE_SWITCH
static ALWAYS_INLINE void
z_set_thread_return_value(struct k_thread *thread, unsigned int value)
{
thread->callee_saved.retval = value;
}
#endif
extern void k_cpu_atomic_idle(unsigned int key); extern void k_cpu_atomic_idle(unsigned int key);
#ifdef __cplusplus #ifdef __cplusplus

View file

@ -15,7 +15,6 @@
* *
* mask - Bit mask of interrupts to be enabled. * mask - Bit mask of interrupts to be enabled.
*/ */
#if CONFIG_XTENSA_ASM2
static inline void z_xt_ints_on(unsigned int mask) static inline void z_xt_ints_on(unsigned int mask)
{ {
int val; int val;
@ -24,9 +23,6 @@ static inline void z_xt_ints_on(unsigned int mask)
val |= mask; val |= mask;
__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
} }
#else
extern void z_xt_ints_on(unsigned int mask);
#endif
/* /*
@ -34,7 +30,6 @@ extern void z_xt_ints_on(unsigned int mask);
* *
* mask - Bit mask of interrupts to be disabled. * mask - Bit mask of interrupts to be disabled.
*/ */
#if CONFIG_XTENSA_ASM2
static inline void z_xt_ints_off(unsigned int mask) static inline void z_xt_ints_off(unsigned int mask)
{ {
int val; int val;
@ -43,9 +38,6 @@ static inline void z_xt_ints_off(unsigned int mask)
val &= ~mask; val &= ~mask;
__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
} }
#else
extern void z_xt_ints_off(unsigned int mask);
#endif
/* /*
* Call this function to set the specified (s/w) interrupt. * Call this function to set the specified (s/w) interrupt.

View file

@ -25,16 +25,8 @@ Hardware
The following Xtensa cores are officially supported: The following Xtensa cores are officially supported:
- hifi3_bd5 - Intel S1000
- XRC_FUSION_AON_ALL_LM - sample_controller
- D_108mini
- D_212GP
- D_233L
- hifi_mini_4swIrq (call0 ABI, added 4 SW IRQ for tests and 1 timer level 1)
- hifi2_std
- XRC_D2PM_5swIrq (added 4 SW IRQ for tests and 1 timer level 1)
- hifi4_bd7 (Big Endian)
- hifi3_bd5_call0 (call0 ABI, added 3 SW IRQs for tests)
System Clock System Clock
============ ============

View file

@ -1,6 +0,0 @@
identifier: xt-sim_D_108mini
name: XT Simulator D_108mini
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_D_108mini=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -1,6 +0,0 @@
identifier: xt-sim_D_212GP
name: XT Simulator D_212GP
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_D_212GP=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -1,6 +0,0 @@
identifier: xt-sim_D_233L
name: XT Simulator D_233L
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_D_233L=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -1,6 +0,0 @@
identifier: xt-sim_XRC_FUSION_AON_ALL_LM
name: XT Simulator XRC_FUSION_AON_ALL_LM
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_XRC_FUSION_AON_ALL_LM=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -1,6 +0,0 @@
identifier: xt-sim_hifi2_std
name: XT Simulatora hifi2_std
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_HIFI2_STD=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -1,6 +0,0 @@
identifier: xt-sim_hifi3_bd5
name: XT Simulator hifi3_bd5
type: sim
arch: xtensa
toolchain:
- xcc

View file

@ -1,13 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
CONFIG_XTENSA=y
CONFIG_SOC_HIFI3_BD5=y
CONFIG_BOARD_XT_SIM=y
CONFIG_CONSOLE=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_SIMULATOR_XTENSA=y

View file

@ -57,17 +57,6 @@ static void ccompare_isr(void *arg)
z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1); z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
} }
/* The legacy Xtensa platform code handles the timer interrupt via a
* special path and must find it via this name. Remove once ASM2 is
* pervasive.
*/
#ifndef CONFIG_XTENSA_ASM2
void timer_int_handler(void *arg)
{
return ccompare_isr(arg);
}
#endif
int z_clock_driver_init(struct device *device) int z_clock_driver_init(struct device *device)
{ {
IRQ_CONNECT(TIMER_IRQ, 0, ccompare_isr, 0, 0); IRQ_CONNECT(TIMER_IRQ, 0, ccompare_isr, 0, 0);

View file

@ -78,11 +78,7 @@ extern void z_irq_priority_set(u32_t irq, u32_t prio, u32_t flags);
/* Spurious interrupt handler. Throws an error if called */ /* Spurious interrupt handler. Throws an error if called */
extern void z_irq_spurious(void *unused); extern void z_irq_spurious(void *unused);
#ifdef CONFIG_XTENSA_ASM2 #define XTENSA_ERR_NORET
#define XTENSA_ERR_NORET /**/
#else
#define XTENSA_ERR_NORET FUNC_NORETURN
#endif
extern u32_t z_timer_cycle_get_32(void); extern u32_t z_timer_cycle_get_32(void);
#define z_arch_k_cycle_get_32() z_timer_cycle_get_32() #define z_arch_k_cycle_get_32() z_timer_cycle_get_32()

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_D_108MINI
config SOC
string
default "D_108mini"
config IRQ_OFFLOAD_INTNUM
default 7
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_D_108MINI
bool "D_108mini core"

View file

@ -1,611 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram0_seg :sram0_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
dram1_0_seg : org = 0x3FFC0000, len = 0x20000
dram0_0_seg : org = 0x3FFE0000, len = 0x20000
iram0_0_seg : org = 0x40000000, len = 0x178
iram0_1_seg : org = 0x40000178, len = 0x8
iram0_2_seg : org = 0x40000180, len = 0x38
iram0_3_seg : org = 0x400001B8, len = 0x8
iram0_4_seg : org = 0x400001C0, len = 0x38
iram0_5_seg : org = 0x400001F8, len = 0x8
iram0_6_seg : org = 0x40000200, len = 0x38
iram0_7_seg : org = 0x40000238, len = 0x8
iram0_8_seg : org = 0x40000240, len = 0x38
iram0_9_seg : org = 0x40000278, len = 0x8
iram0_10_seg : org = 0x40000280, len = 0x38
iram0_11_seg : org = 0x400002B8, len = 0x8
iram0_12_seg : org = 0x400002C0, len = 0x38
iram0_13_seg : org = 0x400002F8, len = 0x8
iram0_14_seg : org = 0x40000300, len = 0x38
iram0_15_seg : org = 0x40000338, len = 0x8
iram0_16_seg : org = 0x40000340, len = 0x38
iram0_17_seg : org = 0x40000378, len = 0x48
iram0_18_seg : org = 0x400003C0, len = 0x40
iram0_19_seg : org = 0x40000400, len = 0x1FC00
srom0_seg : org = 0x50000000, len = 0x300
srom1_seg : org = 0x50000300, len = 0xFFFD00
sram0_seg : org = 0x60000000, len = 0x4000000
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3ffbe000, len = 0x2000
#endif
}
PHDRS
{
dram1_0_phdr PT_LOAD;
dram1_0_bss_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
iram0_1_phdr PT_LOAD;
iram0_2_phdr PT_LOAD;
iram0_3_phdr PT_LOAD;
iram0_4_phdr PT_LOAD;
iram0_5_phdr PT_LOAD;
iram0_6_phdr PT_LOAD;
iram0_7_phdr PT_LOAD;
iram0_8_phdr PT_LOAD;
iram0_9_phdr PT_LOAD;
iram0_10_phdr PT_LOAD;
iram0_11_phdr PT_LOAD;
iram0_12_phdr PT_LOAD;
iram0_13_phdr PT_LOAD;
iram0_14_phdr PT_LOAD;
iram0_15_phdr PT_LOAD;
iram0_16_phdr PT_LOAD;
iram0_17_phdr PT_LOAD;
iram0_18_phdr PT_LOAD;
iram0_19_phdr PT_LOAD;
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram0_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dram1_start = 0x3ffc0000;
_memmap_mem_dram1_end = 0x3ffe0000;
_memmap_mem_dram0_start = 0x3ffe0000;
_memmap_mem_dram0_end = 0x40000000;
_memmap_mem_iram0_start = 0x40000000;
_memmap_mem_iram0_end = 0x40020000;
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_dram1_0_start = 0x3ffc0000;
_memmap_seg_dram1_0_max = 0x3ffe0000;
_memmap_seg_dram0_0_start = 0x3ffe0000;
_memmap_seg_dram0_0_max = 0x40000000;
_memmap_seg_iram0_0_start = 0x40000000;
_memmap_seg_iram0_0_max = 0x40000178;
_memmap_seg_iram0_1_start = 0x40000178;
_memmap_seg_iram0_1_max = 0x40000180;
_memmap_seg_iram0_2_start = 0x40000180;
_memmap_seg_iram0_2_max = 0x400001b8;
_memmap_seg_iram0_3_start = 0x400001b8;
_memmap_seg_iram0_3_max = 0x400001c0;
_memmap_seg_iram0_4_start = 0x400001c0;
_memmap_seg_iram0_4_max = 0x400001f8;
_memmap_seg_iram0_5_start = 0x400001f8;
_memmap_seg_iram0_5_max = 0x40000200;
_memmap_seg_iram0_6_start = 0x40000200;
_memmap_seg_iram0_6_max = 0x40000238;
_memmap_seg_iram0_7_start = 0x40000238;
_memmap_seg_iram0_7_max = 0x40000240;
_memmap_seg_iram0_8_start = 0x40000240;
_memmap_seg_iram0_8_max = 0x40000278;
_memmap_seg_iram0_9_start = 0x40000278;
_memmap_seg_iram0_9_max = 0x40000280;
_memmap_seg_iram0_10_start = 0x40000280;
_memmap_seg_iram0_10_max = 0x400002b8;
_memmap_seg_iram0_11_start = 0x400002b8;
_memmap_seg_iram0_11_max = 0x400002c0;
_memmap_seg_iram0_12_start = 0x400002c0;
_memmap_seg_iram0_12_max = 0x400002f8;
_memmap_seg_iram0_13_start = 0x400002f8;
_memmap_seg_iram0_13_max = 0x40000300;
_memmap_seg_iram0_14_start = 0x40000300;
_memmap_seg_iram0_14_max = 0x40000338;
_memmap_seg_iram0_15_start = 0x40000338;
_memmap_seg_iram0_15_max = 0x40000340;
_memmap_seg_iram0_16_start = 0x40000340;
_memmap_seg_iram0_16_max = 0x40000378;
_memmap_seg_iram0_17_start = 0x40000378;
_memmap_seg_iram0_17_max = 0x400003c0;
_memmap_seg_iram0_18_start = 0x400003c0;
_memmap_seg_iram0_18_max = 0x40000400;
_memmap_seg_iram0_19_start = 0x40000400;
_memmap_seg_iram0_19_max = 0x40020000;
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x50000300;
_memmap_seg_srom1_start = 0x50000300;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x40000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00001110;
_memmap_cacheattr_wt_base = 0x00001110;
_memmap_cacheattr_bp_base = 0x00002220;
_memmap_cacheattr_unused_mask = 0xFFFF000F;
_memmap_cacheattr_wb_trapnull = 0x2222111F;
_memmap_cacheattr_wba_trapnull = 0x2222111F;
_memmap_cacheattr_wbna_trapnull = 0x2222111F;
_memmap_cacheattr_wt_trapnull = 0x2222111F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF111F;
_memmap_cacheattr_wt_strict = 0xFFFF111F;
_memmap_cacheattr_bp_strict = 0xFFFF222F;
_memmap_cacheattr_wb_allvalid = 0x22221112;
_memmap_cacheattr_wt_allvalid = 0x22221112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dram1.rodata : ALIGN(4)
{
_dram1_rodata_start = ABSOLUTE(.);
*(.dram1.rodata)
_dram1_rodata_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.literal : ALIGN(4)
{
_dram1_literal_start = ABSOLUTE(.);
*(.dram1.literal)
_dram1_literal_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.data : ALIGN(4)
{
_dram1_data_start = ABSOLUTE(.);
*(.dram1.data)
_dram1_data_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram1_bss_start = ABSOLUTE(.);
*(.dram1.bss)
. = ALIGN (8);
_dram1_bss_end = ABSOLUTE(.);
_memmap_seg_dram1_0_end = ALIGN(0x8);
} >dram1_0_seg :dram1_0_bss_phdr
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
*(.dram0.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram0_bss_start = ABSOLUTE(.);
*(.dram0.bss)
. = ALIGN (8);
_dram0_bss_end = ABSOLUTE(.);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_1_end = ALIGN(0x8);
} >iram0_1_seg :iram0_1_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_2_end = ALIGN(0x8);
} >iram0_2_seg :iram0_2_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_3_end = ALIGN(0x8);
} >iram0_3_seg :iram0_3_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_4_end = ALIGN(0x8);
} >iram0_4_seg :iram0_4_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_5_end = ALIGN(0x8);
} >iram0_5_seg :iram0_5_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_6_end = ALIGN(0x8);
} >iram0_6_seg :iram0_6_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_7_end = ALIGN(0x8);
} >iram0_7_seg :iram0_7_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_8_end = ALIGN(0x8);
} >iram0_8_seg :iram0_8_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_9_end = ALIGN(0x8);
} >iram0_9_seg :iram0_9_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_10_end = ALIGN(0x8);
} >iram0_10_seg :iram0_10_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_11_end = ALIGN(0x8);
} >iram0_11_seg :iram0_11_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_12_end = ALIGN(0x8);
} >iram0_12_seg :iram0_12_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_13_end = ALIGN(0x8);
} >iram0_13_seg :iram0_13_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_14_end = ALIGN(0x8);
} >iram0_14_seg :iram0_14_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_15_end = ALIGN(0x8);
} >iram0_15_seg :iram0_15_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_16_end = ALIGN(0x8);
} >iram0_16_seg :iram0_16_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_17_end = ALIGN(0x8);
} >iram0_17_seg :iram0_17_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_18_end = ALIGN(0x8);
} >iram0_18_seg :iram0_18_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
_iram0_text_end = ABSOLUTE(.);
_memmap_seg_iram0_19_end = ALIGN(0x8);
} >iram0_19_seg :iram0_19_phdr
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_dram1_bss_start)
LONG(_dram1_bss_end)
LONG(_dram0_bss_start)
LONG(_dram0_bss_end)
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram0_seg :sram0_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram0_seg :sram0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_bss_phdr
__stack = 0x64000000;
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_D_212GP
config SOC
string
default "D_212GP"
config IRQ_OFFLOAD_INTNUM
default 7
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_D_212GP
bool "D_212GP core"

View file

@ -1,617 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram19_seg :sram19_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
dport0_0_seg : org = 0x3FFC0000, len = 0x20000
dram0_0_seg : org = 0x3FFE0000, len = 0x20000
iram0_0_seg : org = 0x40000000, len = 0x20000
srom0_seg : org = 0x50000000, len = 0x300
srom1_seg : org = 0x50000300, len = 0xFFFD00
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x8
sram2_seg : org = 0x60000180, len = 0x38
sram3_seg : org = 0x600001B8, len = 0x8
sram4_seg : org = 0x600001C0, len = 0x38
sram5_seg : org = 0x600001F8, len = 0x8
sram6_seg : org = 0x60000200, len = 0x38
sram7_seg : org = 0x60000238, len = 0x8
sram8_seg : org = 0x60000240, len = 0x38
sram9_seg : org = 0x60000278, len = 0x8
sram10_seg : org = 0x60000280, len = 0x38
sram11_seg : org = 0x600002B8, len = 0x8
sram12_seg : org = 0x600002C0, len = 0x38
sram13_seg : org = 0x600002F8, len = 0x8
sram14_seg : org = 0x60000300, len = 0x38
sram15_seg : org = 0x60000338, len = 0x8
sram16_seg : org = 0x60000340, len = 0x38
sram17_seg : org = 0x60000378, len = 0x48
sram18_seg : org = 0x600003C0, len = 0x40
sram19_seg : org = 0x60000400, len = 0x3FFFC00
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3ffbe000, len = 0x2000
#endif
}
PHDRS
{
dport0_0_phdr PT_LOAD;
dport0_0_bss_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram10_phdr PT_LOAD;
sram11_phdr PT_LOAD;
sram12_phdr PT_LOAD;
sram13_phdr PT_LOAD;
sram14_phdr PT_LOAD;
sram15_phdr PT_LOAD;
sram16_phdr PT_LOAD;
sram17_phdr PT_LOAD;
sram18_phdr PT_LOAD;
sram19_phdr PT_LOAD;
sram19_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dport0_start = 0x3ffc0000;
_memmap_mem_dport0_end = 0x3ffe0000;
_memmap_mem_dram0_start = 0x3ffe0000;
_memmap_mem_dram0_end = 0x40000000;
_memmap_mem_iram0_start = 0x40000000;
_memmap_mem_iram0_end = 0x40020000;
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_dport0_0_start = 0x3ffc0000;
_memmap_seg_dport0_0_max = 0x3ffe0000;
_memmap_seg_dram0_0_start = 0x3ffe0000;
_memmap_seg_dram0_0_max = 0x40000000;
_memmap_seg_iram0_0_start = 0x40000000;
_memmap_seg_iram0_0_max = 0x40020000;
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x50000300;
_memmap_seg_srom1_start = 0x50000300;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x60000180;
_memmap_seg_sram2_start = 0x60000180;
_memmap_seg_sram2_max = 0x600001b8;
_memmap_seg_sram3_start = 0x600001b8;
_memmap_seg_sram3_max = 0x600001c0;
_memmap_seg_sram4_start = 0x600001c0;
_memmap_seg_sram4_max = 0x600001f8;
_memmap_seg_sram5_start = 0x600001f8;
_memmap_seg_sram5_max = 0x60000200;
_memmap_seg_sram6_start = 0x60000200;
_memmap_seg_sram6_max = 0x60000238;
_memmap_seg_sram7_start = 0x60000238;
_memmap_seg_sram7_max = 0x60000240;
_memmap_seg_sram8_start = 0x60000240;
_memmap_seg_sram8_max = 0x60000278;
_memmap_seg_sram9_start = 0x60000278;
_memmap_seg_sram9_max = 0x60000280;
_memmap_seg_sram10_start = 0x60000280;
_memmap_seg_sram10_max = 0x600002b8;
_memmap_seg_sram11_start = 0x600002b8;
_memmap_seg_sram11_max = 0x600002c0;
_memmap_seg_sram12_start = 0x600002c0;
_memmap_seg_sram12_max = 0x600002f8;
_memmap_seg_sram13_start = 0x600002f8;
_memmap_seg_sram13_max = 0x60000300;
_memmap_seg_sram14_start = 0x60000300;
_memmap_seg_sram14_max = 0x60000338;
_memmap_seg_sram15_start = 0x60000338;
_memmap_seg_sram15_max = 0x60000340;
_memmap_seg_sram16_start = 0x60000340;
_memmap_seg_sram16_max = 0x60000378;
_memmap_seg_sram17_start = 0x60000378;
_memmap_seg_sram17_max = 0x600003c0;
_memmap_seg_sram18_start = 0x600003c0;
_memmap_seg_sram18_max = 0x60000400;
_memmap_seg_sram19_start = 0x60000400;
_memmap_seg_sram19_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x60000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00004440;
_memmap_cacheattr_wt_base = 0x00001110;
_memmap_cacheattr_bp_base = 0x00002220;
_memmap_cacheattr_unused_mask = 0xFFFF000F;
_memmap_cacheattr_wb_trapnull = 0x2222444F;
_memmap_cacheattr_wba_trapnull = 0x2222444F;
_memmap_cacheattr_wbna_trapnull = 0x2222555F;
_memmap_cacheattr_wt_trapnull = 0x2222111F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF444F;
_memmap_cacheattr_wt_strict = 0xFFFF111F;
_memmap_cacheattr_bp_strict = 0xFFFF222F;
_memmap_cacheattr_wb_allvalid = 0x22224442;
_memmap_cacheattr_wt_allvalid = 0x22221112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dport0.rodata : ALIGN(4)
{
_dport0_rodata_start = ABSOLUTE(.);
*(.dport0.rodata)
*(.dport.rodata)
_dport0_rodata_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.literal : ALIGN(4)
{
_dport0_literal_start = ABSOLUTE(.);
*(.dport0.literal)
*(.dport.literal)
_dport0_literal_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.data : ALIGN(4)
{
_dport0_data_start = ABSOLUTE(.);
*(.dport0.data)
*(.dport.data)
_dport0_data_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dport0_bss_start = ABSOLUTE(.);
*(.dport0.bss)
. = ALIGN (8);
_dport0_bss_end = ABSOLUTE(.);
_memmap_seg_dport0_0_end = ALIGN(0x8);
} >dport0_0_seg :dport0_0_bss_phdr
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
*(.dram0.rodata)
*(.dram.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
*(.dram.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
*(.dram.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram0_bss_start = ABSOLUTE(.);
*(.dram0.bss)
. = ALIGN (8);
_dram0_bss_end = ABSOLUTE(.);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
_iram0_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram10_end = ALIGN(0x8);
} >sram10_seg :sram10_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram11_end = ALIGN(0x8);
} >sram11_seg :sram11_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram12_end = ALIGN(0x8);
} >sram12_seg :sram12_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram13_end = ALIGN(0x8);
} >sram13_seg :sram13_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram14_end = ALIGN(0x8);
} >sram14_seg :sram14_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram15_end = ALIGN(0x8);
} >sram15_seg :sram15_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram16_end = ALIGN(0x8);
} >sram16_seg :sram16_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram17_end = ALIGN(0x8);
} >sram17_seg :sram17_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram18_end = ALIGN(0x8);
} >sram18_seg :sram18_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_dport0_bss_start)
LONG(_dport0_bss_end)
LONG(_dram0_bss_start)
LONG(_dram0_bss_end)
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram19_seg :sram19_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram19_seg :sram19_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram19_end = ALIGN(0x8);
} >sram19_seg :sram19_bss_phdr
__stack = 0x64000000;
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_D_233L
config SOC
string
default "D_233L"
config IRQ_OFFLOAD_INTNUM
default 7
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_D_233L
bool "D_233L core"

View file

@ -1,519 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram20_seg :sram20_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
sram1_seg : org = 0x00002000, len = 0x178
sram2_seg : org = 0x00002178, len = 0x8
sram3_seg : org = 0x00002180, len = 0x38
sram4_seg : org = 0x000021B8, len = 0x8
sram5_seg : org = 0x000021C0, len = 0x38
sram6_seg : org = 0x000021F8, len = 0x8
sram7_seg : org = 0x00002200, len = 0x38
sram8_seg : org = 0x00002238, len = 0x8
sram9_seg : org = 0x00002240, len = 0x38
sram10_seg : org = 0x00002278, len = 0x8
sram11_seg : org = 0x00002280, len = 0x38
sram12_seg : org = 0x000022B8, len = 0x8
sram13_seg : org = 0x000022C0, len = 0x38
sram14_seg : org = 0x000022F8, len = 0x8
sram15_seg : org = 0x00002300, len = 0x38
sram16_seg : org = 0x00002338, len = 0x8
sram17_seg : org = 0x00002340, len = 0x38
sram18_seg : org = 0x00002378, len = 0x48
sram19_seg : org = 0x000023C0, len = 0x140
sram20_seg : org = 0x00002500, len = 0x3FFDB00
srom0_seg : org = 0xFE000000, len = 0x300
srom1_seg : org = 0xFE000300, len = 0xFFFD00
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3ffdd50, len = 0x2000
#endif
}
PHDRS
{
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram10_phdr PT_LOAD;
sram11_phdr PT_LOAD;
sram12_phdr PT_LOAD;
sram13_phdr PT_LOAD;
sram14_phdr PT_LOAD;
sram15_phdr PT_LOAD;
sram16_phdr PT_LOAD;
sram17_phdr PT_LOAD;
sram18_phdr PT_LOAD;
sram19_phdr PT_LOAD;
sram20_phdr PT_LOAD;
sram20_bss_phdr PT_LOAD;
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_sram_start = 0x4;
_memmap_mem_sram_end = 0x4000000;
_memmap_mem_srom_start = 0xfe000000;
_memmap_mem_srom_end = 0xff000000;
/* Memory segment boundary addresses: */
_memmap_seg_sram1_start = 0x2000;
_memmap_seg_sram1_max = 0x2178;
_memmap_seg_sram2_start = 0x2178;
_memmap_seg_sram2_max = 0x2180;
_memmap_seg_sram3_start = 0x2180;
_memmap_seg_sram3_max = 0x21b8;
_memmap_seg_sram4_start = 0x21b8;
_memmap_seg_sram4_max = 0x21c0;
_memmap_seg_sram5_start = 0x21c0;
_memmap_seg_sram5_max = 0x21f8;
_memmap_seg_sram6_start = 0x21f8;
_memmap_seg_sram6_max = 0x2200;
_memmap_seg_sram7_start = 0x2200;
_memmap_seg_sram7_max = 0x2238;
_memmap_seg_sram8_start = 0x2238;
_memmap_seg_sram8_max = 0x2240;
_memmap_seg_sram9_start = 0x2240;
_memmap_seg_sram9_max = 0x2278;
_memmap_seg_sram10_start = 0x2278;
_memmap_seg_sram10_max = 0x2280;
_memmap_seg_sram11_start = 0x2280;
_memmap_seg_sram11_max = 0x22b8;
_memmap_seg_sram12_start = 0x22b8;
_memmap_seg_sram12_max = 0x22c0;
_memmap_seg_sram13_start = 0x22c0;
_memmap_seg_sram13_max = 0x22f8;
_memmap_seg_sram14_start = 0x22f8;
_memmap_seg_sram14_max = 0x2300;
_memmap_seg_sram15_start = 0x2300;
_memmap_seg_sram15_max = 0x2338;
_memmap_seg_sram16_start = 0x2338;
_memmap_seg_sram16_max = 0x2340;
_memmap_seg_sram17_start = 0x2340;
_memmap_seg_sram17_max = 0x2378;
_memmap_seg_sram18_start = 0x2378;
_memmap_seg_sram18_max = 0x23c0;
_memmap_seg_sram19_start = 0x23c0;
_memmap_seg_sram19_max = 0x2500;
_memmap_seg_sram20_start = 0x2500;
_memmap_seg_sram20_max = 0x4000000;
_memmap_seg_srom0_start = 0xfe000000;
_memmap_seg_srom0_max = 0xfe000300;
_memmap_seg_srom1_start = 0xfe000300;
_memmap_seg_srom1_max = 0xff000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x2000);
PROVIDE(_memmap_reset_vector = 0xfe000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x70000007;
_memmap_cacheattr_wt_base = 0xB000000B;
_memmap_cacheattr_bp_base = 0x30000003;
_memmap_cacheattr_unused_mask = 0x0FFFFFF0;
_memmap_cacheattr_wb_trapnull = 0x73333337;
_memmap_cacheattr_wba_trapnull = 0x73333337;
_memmap_cacheattr_wbna_trapnull = 0x73333337;
_memmap_cacheattr_wt_trapnull = 0xB333333B;
_memmap_cacheattr_bp_trapnull = 0x33333333;
_memmap_cacheattr_wb_strict = 0x7CCCCCC7;
_memmap_cacheattr_wt_strict = 0xBCCCCCCB;
_memmap_cacheattr_bp_strict = 0x3CCCCCC3;
_memmap_cacheattr_wb_allvalid = 0x73333337;
_memmap_cacheattr_wt_allvalid = 0xB333333B;
_memmap_cacheattr_bp_allvalid = 0x33333333;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram10_end = ALIGN(0x8);
} >sram10_seg :sram10_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram11_end = ALIGN(0x8);
} >sram11_seg :sram11_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram12_end = ALIGN(0x8);
} >sram12_seg :sram12_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram13_end = ALIGN(0x8);
} >sram13_seg :sram13_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram14_end = ALIGN(0x8);
} >sram14_seg :sram14_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram15_end = ALIGN(0x8);
} >sram15_seg :sram15_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram16_end = ALIGN(0x8);
} >sram16_seg :sram16_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram17_end = ALIGN(0x8);
} >sram17_seg :sram17_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram18_end = ALIGN(0x8);
} >sram18_seg :sram18_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram19_end = ALIGN(0x8);
} >sram19_seg :sram19_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram20_seg :sram20_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram20_seg :sram20_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram20_seg :sram20_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram20_seg :sram20_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram20_seg :sram20_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram20_seg :sram20_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram20_seg :sram20_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram20_end = ALIGN(0x8);
} >sram20_seg :sram20_bss_phdr
__stack = 0x4000000;
_heap_sentry = 0x4000000;
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_XRC_D2PM_5SWIRQ
config SOC
string
default "XRC_D2PM_5swIrq"
config IRQ_OFFLOAD_INTNUM
default 22
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_XRC_D2PM_5SWIRQ
bool "XRC_D2PM_5swIrq (XRC_D2PM core with 4 additional SW IRQs)"

View file

@ -1,621 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram19_seg :sram19_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
srom0_seg : org = 0x40000000, len = 0x2E0
srom1_seg : org = 0x400002E0, len = 0xFFFD20
dram0_0_seg : org = 0x5FFA0000, len = 0x20000
dram1_0_seg : org = 0x5FFC0000, len = 0x20000
iram0_0_seg : org = 0x5FFE0000, len = 0x20000
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x4
sram2_seg : org = 0x6000017C, len = 0x1C
sram3_seg : org = 0x60000198, len = 0x4
sram4_seg : org = 0x6000019C, len = 0x1C
sram5_seg : org = 0x600001B8, len = 0x4
sram6_seg : org = 0x600001BC, len = 0x1C
sram7_seg : org = 0x600001D8, len = 0x4
sram8_seg : org = 0x600001DC, len = 0x1C
sram9_seg : org = 0x600001F8, len = 0x4
sram10_seg : org = 0x600001FC, len = 0x1C
sram11_seg : org = 0x60000218, len = 0x4
sram12_seg : org = 0x6000021C, len = 0x1C
sram13_seg : org = 0x60000238, len = 0x4
sram14_seg : org = 0x6000023C, len = 0x1C
sram15_seg : org = 0x60000258, len = 0x4
sram16_seg : org = 0x6000025C, len = 0x1C
sram17_seg : org = 0x60000278, len = 0x4
sram18_seg : org = 0x6000027C, len = 0x1C
sram19_seg : org = 0x60000298, len = 0x3FFFD68
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3fffe000, len = 0x2000
#endif
}
PHDRS
{
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
dram1_0_phdr PT_LOAD;
dram1_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram10_phdr PT_LOAD;
sram11_phdr PT_LOAD;
sram12_phdr PT_LOAD;
sram13_phdr PT_LOAD;
sram14_phdr PT_LOAD;
sram15_phdr PT_LOAD;
sram16_phdr PT_LOAD;
sram17_phdr PT_LOAD;
sram18_phdr PT_LOAD;
sram19_phdr PT_LOAD;
sram19_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_srom_start = 0x40000000;
_memmap_mem_srom_end = 0x41000000;
_memmap_mem_dram0_start = 0x5ffa0000;
_memmap_mem_dram0_end = 0x5ffc0000;
_memmap_mem_dram1_start = 0x5ffc0000;
_memmap_mem_dram1_end = 0x5ffe0000;
_memmap_mem_iram0_start = 0x5ffe0000;
_memmap_mem_iram0_end = 0x60000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_srom0_start = 0x40000000;
_memmap_seg_srom0_max = 0x400002e0;
_memmap_seg_srom1_start = 0x400002e0;
_memmap_seg_srom1_max = 0x41000000;
_memmap_seg_dram0_0_start = 0x5ffa0000;
_memmap_seg_dram0_0_max = 0x5ffc0000;
_memmap_seg_dram1_0_start = 0x5ffc0000;
_memmap_seg_dram1_0_max = 0x5ffe0000;
_memmap_seg_iram0_0_start = 0x5ffe0000;
_memmap_seg_iram0_0_max = 0x60000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x6000017c;
_memmap_seg_sram2_start = 0x6000017c;
_memmap_seg_sram2_max = 0x60000198;
_memmap_seg_sram3_start = 0x60000198;
_memmap_seg_sram3_max = 0x6000019c;
_memmap_seg_sram4_start = 0x6000019c;
_memmap_seg_sram4_max = 0x600001b8;
_memmap_seg_sram5_start = 0x600001b8;
_memmap_seg_sram5_max = 0x600001bc;
_memmap_seg_sram6_start = 0x600001bc;
_memmap_seg_sram6_max = 0x600001d8;
_memmap_seg_sram7_start = 0x600001d8;
_memmap_seg_sram7_max = 0x600001dc;
_memmap_seg_sram8_start = 0x600001dc;
_memmap_seg_sram8_max = 0x600001f8;
_memmap_seg_sram9_start = 0x600001f8;
_memmap_seg_sram9_max = 0x600001fc;
_memmap_seg_sram10_start = 0x600001fc;
_memmap_seg_sram10_max = 0x60000218;
_memmap_seg_sram11_start = 0x60000218;
_memmap_seg_sram11_max = 0x6000021c;
_memmap_seg_sram12_start = 0x6000021c;
_memmap_seg_sram12_max = 0x60000238;
_memmap_seg_sram13_start = 0x60000238;
_memmap_seg_sram13_max = 0x6000023c;
_memmap_seg_sram14_start = 0x6000023c;
_memmap_seg_sram14_max = 0x60000258;
_memmap_seg_sram15_start = 0x60000258;
_memmap_seg_sram15_max = 0x6000025c;
_memmap_seg_sram16_start = 0x6000025c;
_memmap_seg_sram16_max = 0x60000278;
_memmap_seg_sram17_start = 0x60000278;
_memmap_seg_sram17_max = 0x6000027c;
_memmap_seg_sram18_start = 0x6000027c;
_memmap_seg_sram18_max = 0x60000298;
_memmap_seg_sram19_start = 0x60000298;
_memmap_seg_sram19_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x60000000);
PROVIDE(_memmap_reset_vector = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00001100;
_memmap_cacheattr_wt_base = 0x00001100;
_memmap_cacheattr_bp_base = 0x00002200;
_memmap_cacheattr_unused_mask = 0xFFFF00FF;
_memmap_cacheattr_wb_trapnull = 0x2222112F;
_memmap_cacheattr_wba_trapnull = 0x2222112F;
_memmap_cacheattr_wbna_trapnull = 0x2222112F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF11FF;
_memmap_cacheattr_wt_strict = 0xFFFF11FF;
_memmap_cacheattr_bp_strict = 0xFFFF22FF;
_memmap_cacheattr_wb_allvalid = 0x22221122;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
} >srom1_seg :srom1_phdr
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
*(.dram0.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram0_bss_start = ABSOLUTE(.);
*(.dram0.bss)
. = ALIGN (8);
_dram0_bss_end = ABSOLUTE(.);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
.dram1.rodata : ALIGN(4)
{
_dram1_rodata_start = ABSOLUTE(.);
*(.dram1.rodata)
_dram1_rodata_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.iram0.literal : ALIGN(4)
{
_iram0_literal_start = ABSOLUTE(.);
*(.iram0.literal)
*(.iram.literal)
*(.iram.text.literal)
_iram0_literal_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.literal : ALIGN(4)
{
_dram1_literal_start = ABSOLUTE(.);
*(.dram1.literal)
_dram1_literal_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.data : ALIGN(4)
{
_dram1_data_start = ABSOLUTE(.);
*(.dram1.data)
_dram1_data_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram1_bss_start = ABSOLUTE(.);
*(.dram1.bss)
. = ALIGN (8);
_dram1_bss_end = ABSOLUTE(.);
_memmap_seg_dram1_0_end = ALIGN(0x8);
} >dram1_0_seg :dram1_0_bss_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.text)
*(.iram.text)
_iram0_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >iram0_0_seg :iram0_0_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram10_end = ALIGN(0x8);
} >sram10_seg :sram10_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram11_end = ALIGN(0x8);
} >sram11_seg :sram11_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram12_end = ALIGN(0x8);
} >sram12_seg :sram12_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram13_end = ALIGN(0x8);
} >sram13_seg :sram13_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram14_end = ALIGN(0x8);
} >sram14_seg :sram14_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram15_end = ALIGN(0x8);
} >sram15_seg :sram15_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram16_end = ALIGN(0x8);
} >sram16_seg :sram16_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram17_end = ALIGN(0x8);
} >sram17_seg :sram17_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram18_end = ALIGN(0x8);
} >sram18_seg :sram18_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_dram0_bss_start)
LONG(_dram0_bss_end)
LONG(_dram1_bss_start)
LONG(_dram1_bss_end)
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram19_seg :sram19_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram19_seg :sram19_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram19_end = ALIGN(0x8);
} >sram19_seg :sram19_bss_phdr
PROVIDE(__stack = 0x64000000);
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_XRC_FUSION_AON_ALL_LM
config SOC
string
default "XRC_FUSION_AON_ALL_LM"
config IRQ_OFFLOAD_INTNUM
default 13
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_XRC_FUSION_AON_ALL_LM
bool "XRC_FUSION_AON_ALL_LM core"

View file

@ -1,450 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram0_seg :sram0_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
dram0_0_seg : org = 0x3FFE0000, len = 0x20000
iram0_0_seg : org = 0x40000000, len = 0x178
iram0_2_seg : org = 0x40000180, len = 0x38
iram0_4_seg : org = 0x400001C0, len = 0x38
iram0_6_seg : org = 0x40000200, len = 0x38
iram0_8_seg : org = 0x40000280, len = 0x40
iram0_9_seg : org = 0x400002C0, len = 0x1FD40
srom0_seg : org = 0x50000000, len = 0x300
srom1_seg : org = 0x50000300, len = 0xFFFD00
sram0_seg : org = 0x60000000, len = 0x4000000
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3ffde000, len = 0x2000
#endif
}
PHDRS
{
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
iram0_1_phdr PT_LOAD;
iram0_2_phdr PT_LOAD;
iram0_3_phdr PT_LOAD;
iram0_4_phdr PT_LOAD;
iram0_5_phdr PT_LOAD;
iram0_6_phdr PT_LOAD;
iram0_7_phdr PT_LOAD;
iram0_8_phdr PT_LOAD;
iram0_9_phdr PT_LOAD;
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram0_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dram0_start = 0x3ffe0000;
_memmap_mem_dram0_end = 0x40000000;
_memmap_mem_iram0_start = 0x40000000;
_memmap_mem_iram0_end = 0x40020000;
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_dram0_0_start = 0x3ffe0000;
_memmap_seg_dram0_0_max = 0x40000000;
_memmap_seg_iram0_0_start = 0x40000000;
_memmap_seg_iram0_0_max = 0x40000178;
_memmap_seg_iram0_2_start = 0x40000180;
_memmap_seg_iram0_2_max = 0x400001b8;
_memmap_seg_iram0_4_start = 0x400001c0;
_memmap_seg_iram0_4_max = 0x400001f8;
_memmap_seg_iram0_6_start = 0x40000200;
_memmap_seg_iram0_6_max = 0x40000238;
_memmap_seg_iram0_8_start = 0x40000280;
_memmap_seg_iram0_8_max = 0x400002c0;
_memmap_seg_iram0_9_start = 0x400002c0;
_memmap_seg_iram0_9_max = 0x40020000;
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x50000300;
_memmap_seg_srom1_start = 0x50000300;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x40000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00001120;
_memmap_cacheattr_wt_base = 0x00001120;
_memmap_cacheattr_bp_base = 0x00002220;
_memmap_cacheattr_unused_mask = 0xFFFF000F;
_memmap_cacheattr_wb_trapnull = 0x2222112F;
_memmap_cacheattr_wba_trapnull = 0x2222112F;
_memmap_cacheattr_wbna_trapnull = 0x2222112F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF112F;
_memmap_cacheattr_wt_strict = 0xFFFF112F;
_memmap_cacheattr_bp_strict = 0xFFFF222F;
_memmap_cacheattr_wb_allvalid = 0x22221122;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
*(.dram0.rodata)
*(.dram.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.iram0.literal : ALIGN(4)
{
_iram0_literal_start = ABSOLUTE(.);
*(.iram0.literal)
*(.iram.literal)
*(.iram.text.literal)
_iram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
*(.dram.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
*(.dram.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram0_bss_start = ABSOLUTE(.);
*(.dram0.bss)
. = ALIGN (8);
_dram0_bss_end = ABSOLUTE(.);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_2_end = ALIGN(0x8);
} >iram0_2_seg :iram0_2_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_4_end = ALIGN(0x8);
} >iram0_4_seg :iram0_4_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_6_end = ALIGN(0x8);
} >iram0_6_seg :iram0_6_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_8_end = ALIGN(0x8);
} >iram0_8_seg :iram0_8_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.text)
*(.iram.text)
_iram0_text_end = ABSOLUTE(.);
_memmap_seg_iram0_9_end = ALIGN(0x8);
} >iram0_9_seg :iram0_9_phdr
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_dram0_bss_start)
LONG(_dram0_bss_end)
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram0_seg :sram0_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram0_seg :sram0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram0_seg :sram0_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_image_ram_end = ABSOLUTE(.);
_end = ALIGN(0x8);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_bss_phdr
PROVIDE(__stack = 0x64000000);
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -12,9 +12,6 @@ config SOC
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM
default 7 default 7
config XTENSA_ASM2
default y
config MP_NUM_CPUS config MP_NUM_CPUS
default 2 default 2

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI2_STD
config SOC
string
default "hifi2_std"
config IRQ_OFFLOAD_INTNUM
default 7
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI2_STD
bool "hifi2_std core"

View file

@ -1,621 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram19_seg :sram19_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
dram1_0_seg : org = 0x3FFC0000, len = 0x20000
dram0_0_seg : org = 0x3FFE0000, len = 0x20000
iram0_0_seg : org = 0x40000000, len = 0x20000
srom0_seg : org = 0x50000000, len = 0x300
srom1_seg : org = 0x50000300, len = 0xFFFD00
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x8
sram2_seg : org = 0x60000180, len = 0x38
sram3_seg : org = 0x600001B8, len = 0x8
sram4_seg : org = 0x600001C0, len = 0x38
sram5_seg : org = 0x600001F8, len = 0x8
sram6_seg : org = 0x60000200, len = 0x38
sram7_seg : org = 0x60000238, len = 0x8
sram8_seg : org = 0x60000240, len = 0x38
sram9_seg : org = 0x60000278, len = 0x8
sram10_seg : org = 0x60000280, len = 0x38
sram11_seg : org = 0x600002B8, len = 0x8
sram12_seg : org = 0x600002C0, len = 0x38
sram13_seg : org = 0x600002F8, len = 0x8
sram14_seg : org = 0x60000300, len = 0x38
sram15_seg : org = 0x60000338, len = 0x8
sram16_seg : org = 0x60000340, len = 0x38
sram17_seg : org = 0x60000378, len = 0x48
sram18_seg : org = 0x600003C0, len = 0x40
sram19_seg : org = 0x60000400, len = 0x3FFFC00
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x3ffbe000, len = 0x2000
#endif
}
PHDRS
{
dram1_0_phdr PT_LOAD;
dram1_0_bss_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram10_phdr PT_LOAD;
sram11_phdr PT_LOAD;
sram12_phdr PT_LOAD;
sram13_phdr PT_LOAD;
sram14_phdr PT_LOAD;
sram15_phdr PT_LOAD;
sram16_phdr PT_LOAD;
sram17_phdr PT_LOAD;
sram18_phdr PT_LOAD;
sram19_phdr PT_LOAD;
sram19_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dram1_start = 0x3ffc0000;
_memmap_mem_dram1_end = 0x3ffe0000;
_memmap_mem_dram0_start = 0x3ffe0000;
_memmap_mem_dram0_end = 0x40000000;
_memmap_mem_iram0_start = 0x40000000;
_memmap_mem_iram0_end = 0x40020000;
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_dram1_0_start = 0x3ffc0000;
_memmap_seg_dram1_0_max = 0x3ffe0000;
_memmap_seg_dram0_0_start = 0x3ffe0000;
_memmap_seg_dram0_0_max = 0x40000000;
_memmap_seg_iram0_0_start = 0x40000000;
_memmap_seg_iram0_0_max = 0x40020000;
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x50000300;
_memmap_seg_srom1_start = 0x50000300;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x60000180;
_memmap_seg_sram2_start = 0x60000180;
_memmap_seg_sram2_max = 0x600001b8;
_memmap_seg_sram3_start = 0x600001b8;
_memmap_seg_sram3_max = 0x600001c0;
_memmap_seg_sram4_start = 0x600001c0;
_memmap_seg_sram4_max = 0x600001f8;
_memmap_seg_sram5_start = 0x600001f8;
_memmap_seg_sram5_max = 0x60000200;
_memmap_seg_sram6_start = 0x60000200;
_memmap_seg_sram6_max = 0x60000238;
_memmap_seg_sram7_start = 0x60000238;
_memmap_seg_sram7_max = 0x60000240;
_memmap_seg_sram8_start = 0x60000240;
_memmap_seg_sram8_max = 0x60000278;
_memmap_seg_sram9_start = 0x60000278;
_memmap_seg_sram9_max = 0x60000280;
_memmap_seg_sram10_start = 0x60000280;
_memmap_seg_sram10_max = 0x600002b8;
_memmap_seg_sram11_start = 0x600002b8;
_memmap_seg_sram11_max = 0x600002c0;
_memmap_seg_sram12_start = 0x600002c0;
_memmap_seg_sram12_max = 0x600002f8;
_memmap_seg_sram13_start = 0x600002f8;
_memmap_seg_sram13_max = 0x60000300;
_memmap_seg_sram14_start = 0x60000300;
_memmap_seg_sram14_max = 0x60000338;
_memmap_seg_sram15_start = 0x60000338;
_memmap_seg_sram15_max = 0x60000340;
_memmap_seg_sram16_start = 0x60000340;
_memmap_seg_sram16_max = 0x60000378;
_memmap_seg_sram17_start = 0x60000378;
_memmap_seg_sram17_max = 0x600003c0;
_memmap_seg_sram18_start = 0x600003c0;
_memmap_seg_sram18_max = 0x60000400;
_memmap_seg_sram19_start = 0x60000400;
_memmap_seg_sram19_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x60000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00004420;
_memmap_cacheattr_wt_base = 0x00001120;
_memmap_cacheattr_bp_base = 0x00002220;
_memmap_cacheattr_unused_mask = 0xFFFF000F;
_memmap_cacheattr_wb_trapnull = 0x2222442F;
_memmap_cacheattr_wba_trapnull = 0x2222442F;
_memmap_cacheattr_wbna_trapnull = 0x2222552F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF442F;
_memmap_cacheattr_wt_strict = 0xFFFF112F;
_memmap_cacheattr_bp_strict = 0xFFFF222F;
_memmap_cacheattr_wb_allvalid = 0x22224422;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dram1.rodata : ALIGN(4)
{
_dram1_rodata_start = ABSOLUTE(.);
*(.dram1.rodata)
_dram1_rodata_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.literal : ALIGN(4)
{
_dram1_literal_start = ABSOLUTE(.);
*(.dram1.literal)
_dram1_literal_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.data : ALIGN(4)
{
_dram1_data_start = ABSOLUTE(.);
*(.dram1.data)
_dram1_data_end = ABSOLUTE(.);
} >dram1_0_seg :dram1_0_phdr
.dram1.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram1_bss_start = ABSOLUTE(.);
*(.dram1.bss)
. = ALIGN (8);
_dram1_bss_end = ABSOLUTE(.);
_memmap_seg_dram1_0_end = ALIGN(0x8);
} >dram1_0_seg :dram1_0_bss_phdr
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
*(.dram0.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.iram0.literal : ALIGN(4)
{
_iram0_literal_start = ABSOLUTE(.);
*(.iram0.literal)
*(.iram.literal)
*(.iram.text.literal)
_iram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_dram0_bss_start = ABSOLUTE(.);
*(.dram0.bss)
. = ALIGN (8);
_dram0_bss_end = ABSOLUTE(.);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.text)
*(.iram.text)
_iram0_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.Level5InterruptVector.literal : ALIGN(4)
{
_Level5InterruptVector_literal_start = ABSOLUTE(.);
*(.Level5InterruptVector.literal)
_Level5InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.Level5InterruptVector.text : ALIGN(4)
{
_Level5InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level5InterruptVector.text))
_Level5InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram10_end = ALIGN(0x8);
} >sram10_seg :sram10_phdr
.NMIExceptionVector.literal : ALIGN(4)
{
_NMIExceptionVector_literal_start = ABSOLUTE(.);
*(.NMIExceptionVector.literal)
_NMIExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram11_end = ALIGN(0x8);
} >sram11_seg :sram11_phdr
.NMIExceptionVector.text : ALIGN(4)
{
_NMIExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.NMIExceptionVector.text))
_NMIExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram12_end = ALIGN(0x8);
} >sram12_seg :sram12_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram13_end = ALIGN(0x8);
} >sram13_seg :sram13_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram14_end = ALIGN(0x8);
} >sram14_seg :sram14_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram15_end = ALIGN(0x8);
} >sram15_seg :sram15_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram16_end = ALIGN(0x8);
} >sram16_seg :sram16_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram17_end = ALIGN(0x8);
} >sram17_seg :sram17_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram18_end = ALIGN(0x8);
} >sram18_seg :sram18_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_dram1_bss_start)
LONG(_dram1_bss_end)
LONG(_dram0_bss_start)
LONG(_dram0_bss_end)
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram19_seg :sram19_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram19_seg :sram19_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram19_seg :sram19_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram19_end = ALIGN(0x8);
} >sram19_seg :sram19_bss_phdr
PROVIDE(__stack = 0x64000000);
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI3_BD5
config SOC
string
default "hifi3_bd5"
config IRQ_OFFLOAD_INTNUM
default 13
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI3_BD5
bool "hifi3_bd5 core"

View file

@ -1,397 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram9_seg :sram9_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
srom0_seg : org = 0x50000000, len = 0x2E0
srom1_seg : org = 0x500002E0, len = 0xFFFD20
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x4
sram2_seg : org = 0x6000017C, len = 0x1C
sram3_seg : org = 0x60000198, len = 0x4
sram4_seg : org = 0x6000019C, len = 0x1C
sram5_seg : org = 0x600001B8, len = 0x4
sram6_seg : org = 0x600001BC, len = 0x1C
sram7_seg : org = 0x600001D8, len = 0x4
sram8_seg : org = 0x600001DC, len = 0x1C
sram9_seg : org = 0x600001F8, len = 0x3FFFE08
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x4fffe000, len = 0x2000
#endif
}
PHDRS
{
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram9_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x500002e0;
_memmap_seg_srom1_start = 0x500002e0;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x6000017c;
_memmap_seg_sram2_start = 0x6000017c;
_memmap_seg_sram2_max = 0x60000198;
_memmap_seg_sram3_start = 0x60000198;
_memmap_seg_sram3_max = 0x6000019c;
_memmap_seg_sram4_start = 0x6000019c;
_memmap_seg_sram4_max = 0x600001b8;
_memmap_seg_sram5_start = 0x600001b8;
_memmap_seg_sram5_max = 0x600001bc;
_memmap_seg_sram6_start = 0x600001bc;
_memmap_seg_sram6_max = 0x600001d8;
_memmap_seg_sram7_start = 0x600001d8;
_memmap_seg_sram7_max = 0x600001dc;
_memmap_seg_sram8_start = 0x600001dc;
_memmap_seg_sram8_max = 0x600001f8;
_memmap_seg_sram9_start = 0x600001f8;
_memmap_seg_sram9_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x60000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00004400;
_memmap_cacheattr_wt_base = 0x00001100;
_memmap_cacheattr_bp_base = 0x00002200;
_memmap_cacheattr_unused_mask = 0xFFFF00FF;
_memmap_cacheattr_wb_trapnull = 0x2222442F;
_memmap_cacheattr_wba_trapnull = 0x2222442F;
_memmap_cacheattr_wbna_trapnull = 0x2222552F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF44FF;
_memmap_cacheattr_wt_strict = 0xFFFF11FF;
_memmap_cacheattr_bp_strict = 0xFFFF22FF;
_memmap_cacheattr_wb_allvalid = 0x22224422;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram9_seg :sram9_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram9_seg :sram9_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_bss_phdr
__stack = 0x64000000;
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI3_BD5_CALL0
config SOC
string
default "hifi3_bd5_call0"
config IRQ_OFFLOAD_INTNUM
default 13
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI3_BD5_CALL0
bool "hifi3_bd5_call0 (hifi3_bd5 core with call0 ABI and 3 additional SW IRQs)"

View file

@ -1,397 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram9_seg :sram9_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
srom0_seg : org = 0x50000000, len = 0x2E0
srom1_seg : org = 0x500002E0, len = 0xFFFD20
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x4
sram2_seg : org = 0x6000017C, len = 0x1C
sram3_seg : org = 0x60000198, len = 0x4
sram4_seg : org = 0x6000019C, len = 0x1C
sram5_seg : org = 0x600001B8, len = 0x4
sram6_seg : org = 0x600001BC, len = 0x1C
sram7_seg : org = 0x600001D8, len = 0x4
sram8_seg : org = 0x600001DC, len = 0x1C
sram9_seg : org = 0x600001F8, len = 0x3FFFE08
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x4fffe000, len = 0x2000
#endif
}
PHDRS
{
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram9_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x51000000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x64000000;
/* Memory segment boundary addresses: */
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x500002e0;
_memmap_seg_srom1_start = 0x500002e0;
_memmap_seg_srom1_max = 0x51000000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x6000017c;
_memmap_seg_sram2_start = 0x6000017c;
_memmap_seg_sram2_max = 0x60000198;
_memmap_seg_sram3_start = 0x60000198;
_memmap_seg_sram3_max = 0x6000019c;
_memmap_seg_sram4_start = 0x6000019c;
_memmap_seg_sram4_max = 0x600001b8;
_memmap_seg_sram5_start = 0x600001b8;
_memmap_seg_sram5_max = 0x600001bc;
_memmap_seg_sram6_start = 0x600001bc;
_memmap_seg_sram6_max = 0x600001d8;
_memmap_seg_sram7_start = 0x600001d8;
_memmap_seg_sram7_max = 0x600001dc;
_memmap_seg_sram8_start = 0x600001dc;
_memmap_seg_sram8_max = 0x600001f8;
_memmap_seg_sram9_start = 0x600001f8;
_memmap_seg_sram9_max = 0x64000000;
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = 0x60000000);
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00004400;
_memmap_cacheattr_wt_base = 0x00001100;
_memmap_cacheattr_bp_base = 0x00002200;
_memmap_cacheattr_unused_mask = 0xFFFF00FF;
_memmap_cacheattr_wb_trapnull = 0x2222442F;
_memmap_cacheattr_wba_trapnull = 0x2222442F;
_memmap_cacheattr_wbna_trapnull = 0x2222552F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF44FF;
_memmap_cacheattr_wt_strict = 0xFFFF11FF;
_memmap_cacheattr_bp_strict = 0xFFFF22FF;
_memmap_cacheattr_wb_allvalid = 0x22224422;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.DebugExceptionVector.literal : ALIGN(4)
{
_DebugExceptionVector_literal_start = ABSOLUTE(.);
*(.DebugExceptionVector.literal)
_DebugExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.DebugExceptionVector.text : ALIGN(4)
{
_DebugExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DebugExceptionVector.text))
_DebugExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram9_seg :sram9_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram9_seg :sram9_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram9_seg :sram9_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_bss_phdr
__stack = 0x64000000;
_heap_sentry = 0x64000000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI4_BD7
config SOC
string
default "hifi4_bd7"
config IRQ_OFFLOAD_INTNUM
default 4
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI4_BD7
bool "hifi4_bd7 core"

View file

@ -1,444 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram13_seg :sram13_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
srom0_seg : org = 0x50000000, len = 0x300
srom1_seg : org = 0x50000300, len = 0x1FD00
sram0_seg : org = 0x60000000, len = 0x178
sram1_seg : org = 0x60000178, len = 0x8
sram2_seg : org = 0x60000180, len = 0x38
sram3_seg : org = 0x600001B8, len = 0x8
sram4_seg : org = 0x600001C0, len = 0x38
sram5_seg : org = 0x600001F8, len = 0x8
sram6_seg : org = 0x60000200, len = 0x38
sram7_seg : org = 0x60000238, len = 0x8
sram8_seg : org = 0x60000240, len = 0x38
sram9_seg : org = 0x60000278, len = 0x8
sram10_seg : org = 0x60000280, len = 0x38
sram11_seg : org = 0x600002B8, len = 0x48
sram12_seg : org = 0x60000300, len = 0x40
sram13_seg : org = 0x60000340, len = 0x3FFCC0
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x4fffe000, len = 0x2000
#endif
}
PHDRS
{
srom0_phdr PT_LOAD;
srom1_phdr PT_LOAD;
sram0_phdr PT_LOAD;
sram1_phdr PT_LOAD;
sram2_phdr PT_LOAD;
sram3_phdr PT_LOAD;
sram4_phdr PT_LOAD;
sram5_phdr PT_LOAD;
sram6_phdr PT_LOAD;
sram7_phdr PT_LOAD;
sram8_phdr PT_LOAD;
sram9_phdr PT_LOAD;
sram10_phdr PT_LOAD;
sram11_phdr PT_LOAD;
sram12_phdr PT_LOAD;
sram13_phdr PT_LOAD;
sram13_bss_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_srom_start = 0x50000000;
_memmap_mem_srom_end = 0x50020000;
_memmap_mem_sram_start = 0x60000000;
_memmap_mem_sram_end = 0x60400000;
/* Memory segment boundary addresses: */
_memmap_seg_srom0_start = 0x50000000;
_memmap_seg_srom0_max = 0x50000300;
_memmap_seg_srom1_start = 0x50000300;
_memmap_seg_srom1_max = 0x50020000;
_memmap_seg_sram0_start = 0x60000000;
_memmap_seg_sram0_max = 0x60000178;
_memmap_seg_sram1_start = 0x60000178;
_memmap_seg_sram1_max = 0x60000180;
_memmap_seg_sram2_start = 0x60000180;
_memmap_seg_sram2_max = 0x600001b8;
_memmap_seg_sram3_start = 0x600001b8;
_memmap_seg_sram3_max = 0x600001c0;
_memmap_seg_sram4_start = 0x600001c0;
_memmap_seg_sram4_max = 0x600001f8;
_memmap_seg_sram5_start = 0x600001f8;
_memmap_seg_sram5_max = 0x60000200;
_memmap_seg_sram6_start = 0x60000200;
_memmap_seg_sram6_max = 0x60000238;
_memmap_seg_sram7_start = 0x60000238;
_memmap_seg_sram7_max = 0x60000240;
_memmap_seg_sram8_start = 0x60000240;
_memmap_seg_sram8_max = 0x60000278;
_memmap_seg_sram9_start = 0x60000278;
_memmap_seg_sram9_max = 0x60000280;
_memmap_seg_sram10_start = 0x60000280;
_memmap_seg_sram10_max = 0x600002b8;
_memmap_seg_sram11_start = 0x600002b8;
_memmap_seg_sram11_max = 0x60000300;
_memmap_seg_sram12_start = 0x60000300;
_memmap_seg_sram12_max = 0x60000340;
_memmap_seg_sram13_start = 0x60000340;
_memmap_seg_sram13_max = 0x60400000;
_rom_store_table = 0;
PROVIDE(_memmap_reset_vector = 0x50000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00004400;
_memmap_cacheattr_wt_base = 0x00001100;
_memmap_cacheattr_bp_base = 0x00002200;
_memmap_cacheattr_unused_mask = 0xFFFF00FF;
_memmap_cacheattr_wb_trapnull = 0x2222442F;
_memmap_cacheattr_wba_trapnull = 0x2222442F;
_memmap_cacheattr_wbna_trapnull = 0x2222552F;
_memmap_cacheattr_wt_trapnull = 0x2222112F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF44FF;
_memmap_cacheattr_wt_strict = 0xFFFF11FF;
_memmap_cacheattr_bp_strict = 0xFFFF22FF;
_memmap_cacheattr_wb_allvalid = 0x22224422;
_memmap_cacheattr_wt_allvalid = 0x22221122;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_srom0_end = ALIGN(0x8);
} >srom0_seg :srom0_phdr
.srom.rodata : ALIGN(4)
{
_srom_rodata_start = ABSOLUTE(.);
*(.srom.rodata)
_srom_rodata_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.srom.text : ALIGN(4)
{
_srom_text_start = ABSOLUTE(.);
*(.srom.literal .srom.text)
_srom_text_end = ABSOLUTE(.);
_memmap_seg_srom1_end = ALIGN(0x8);
_image_rom_end = ABSOLUTE(.);
} >srom1_seg :srom1_phdr
.WindowVectors.text : ALIGN(4)
{
_WindowVectors_text_start = ABSOLUTE(.);
KEEP (*(.WindowVectors.text))
_WindowVectors_text_end = ABSOLUTE(.);
_memmap_seg_sram0_end = ALIGN(0x8);
} >sram0_seg :sram0_phdr
.Level2InterruptVector.literal : ALIGN(4)
{
_Level2InterruptVector_literal_start = ABSOLUTE(.);
*(.Level2InterruptVector.literal)
_Level2InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram1_end = ALIGN(0x8);
} >sram1_seg :sram1_phdr
.Level2InterruptVector.text : ALIGN(4)
{
_Level2InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level2InterruptVector.text))
_Level2InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram2_end = ALIGN(0x8);
} >sram2_seg :sram2_phdr
.Level3InterruptVector.literal : ALIGN(4)
{
_Level3InterruptVector_literal_start = ABSOLUTE(.);
*(.Level3InterruptVector.literal)
_Level3InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram3_end = ALIGN(0x8);
} >sram3_seg :sram3_phdr
.Level3InterruptVector.text : ALIGN(4)
{
_Level3InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level3InterruptVector.text))
_Level3InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram4_end = ALIGN(0x8);
} >sram4_seg :sram4_phdr
.Level4InterruptVector.literal : ALIGN(4)
{
_Level4InterruptVector_literal_start = ABSOLUTE(.);
*(.Level4InterruptVector.literal)
_Level4InterruptVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram5_end = ALIGN(0x8);
} >sram5_seg :sram5_phdr
.Level4InterruptVector.text : ALIGN(4)
{
_Level4InterruptVector_text_start = ABSOLUTE(.);
KEEP (*(.Level4InterruptVector.text))
_Level4InterruptVector_text_end = ABSOLUTE(.);
_memmap_seg_sram6_end = ALIGN(0x8);
} >sram6_seg :sram6_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram7_end = ALIGN(0x8);
} >sram7_seg :sram7_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram8_end = ALIGN(0x8);
} >sram8_seg :sram8_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram9_end = ALIGN(0x8);
} >sram9_seg :sram9_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram10_end = ALIGN(0x8);
} >sram10_seg :sram10_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_sram11_end = ALIGN(0x8);
} >sram11_seg :sram11_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_sram12_end = ALIGN(0x8);
} >sram12_seg :sram12_phdr
.sram.rodata : ALIGN(4)
{
_image_ram_start = ABSOLUTE(.);
_sram_rodata_start = ABSOLUTE(.);
*(.sram.rodata)
_sram_rodata_end = ABSOLUTE(.);
} >sram13_seg :sram13_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >sram13_seg :sram13_phdr
.sram.text : ALIGN(4)
{
_sram_text_start = ABSOLUTE(.);
*(.sram.literal .sram.text)
_sram_text_end = ABSOLUTE(.);
} >sram13_seg :sram13_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >sram13_seg :sram13_phdr
_image_text_end = .;
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >sram13_seg :sram13_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >sram13_seg :sram13_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >sram13_seg :sram13_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.sram.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_sram13_end = ALIGN(0x8);
} >sram13_seg :sram13_bss_phdr
__stack = 0x60400000;
_heap_sentry = 0x60400000;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI_MINI
config SOC
string
default "hifi_mini"
config IRQ_OFFLOAD_INTNUM
default 13
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI_MINI
bool "hifi_mini core"

View file

@ -1,369 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr
#define ROMABLE_REGION iram0_7_seg :iram0_7_phdr
MEMORY
{
dram0_0_seg : org = 0x60000000, len = 0x20000
iram0_0_seg : org = 0x60020000, len = 0x2E0
iram0_1_seg : org = 0x600202E0, len = 0x4
iram0_2_seg : org = 0x600202E4, len = 0x1C
iram0_3_seg : org = 0x60020300, len = 0x4
iram0_4_seg : org = 0x60020304, len = 0x1C
iram0_5_seg : org = 0x60020320, len = 0x4
iram0_6_seg : org = 0x60020324, len = 0x1C
iram0_7_seg : org = 0x60020340, len = 0x1FCC0
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x5fffe000, len = 0x2000
#endif
}
PHDRS
{
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
iram0_1_phdr PT_LOAD;
iram0_2_phdr PT_LOAD;
iram0_3_phdr PT_LOAD;
iram0_4_phdr PT_LOAD;
iram0_5_phdr PT_LOAD;
iram0_6_phdr PT_LOAD;
iram0_7_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dram0_start = 0x60000000;
_memmap_mem_dram0_end = 0x60020000;
_memmap_mem_iram0_start = 0x60020000;
_memmap_mem_iram0_end = 0x60040000;
/* Memory segment boundary addresses: */
_memmap_seg_dram0_0_start = 0x60000000;
_memmap_seg_dram0_0_max = 0x60020000;
_memmap_seg_iram0_0_start = 0x60020000;
_memmap_seg_iram0_0_max = 0x600202e0;
_memmap_seg_iram0_1_start = 0x600202e0;
_memmap_seg_iram0_1_max = 0x600202e4;
_memmap_seg_iram0_2_start = 0x600202e4;
_memmap_seg_iram0_2_max = 0x60020300;
_memmap_seg_iram0_3_start = 0x60020300;
_memmap_seg_iram0_3_max = 0x60020304;
_memmap_seg_iram0_4_start = 0x60020304;
_memmap_seg_iram0_4_max = 0x60020320;
_memmap_seg_iram0_5_start = 0x60020320;
_memmap_seg_iram0_5_max = 0x60020324;
_memmap_seg_iram0_6_start = 0x60020324;
_memmap_seg_iram0_6_max = 0x60020340;
_memmap_seg_iram0_7_start = 0x60020340;
_memmap_seg_iram0_7_max = 0x60040000;
_rom_store_table = 0;
PROVIDE(_memmap_reset_vector = 0x60020000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00001000;
_memmap_cacheattr_wt_base = 0x00001000;
_memmap_cacheattr_bp_base = 0x00002000;
_memmap_cacheattr_unused_mask = 0xFFFF0FFF;
_memmap_cacheattr_wb_trapnull = 0x2222122F;
_memmap_cacheattr_wba_trapnull = 0x2222122F;
_memmap_cacheattr_wbna_trapnull = 0x2222122F;
_memmap_cacheattr_wt_trapnull = 0x2222122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF1FFF;
_memmap_cacheattr_wt_strict = 0xFFFF1FFF;
_memmap_cacheattr_bp_strict = 0xFFFF2FFF;
_memmap_cacheattr_wb_allvalid = 0x22221222;
_memmap_cacheattr_wt_allvalid = 0x22221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
_image_ram_start = ABSOLUTE(.);
*(.dram0.rodata)
*(.dram.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
*(.dram.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.ResetVector.literal : ALIGN(4)
{
_ResetVector_literal_start = ABSOLUTE(.);
*(.ResetVector.literal)
_ResetVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
*(.dram.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >dram0_0_seg :dram0_0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.dram0.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
__stack = 0x60020000;
_heap_sentry = 0x60020000;
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_1_end = ALIGN(0x8);
} >iram0_1_seg :iram0_1_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_2_end = ALIGN(0x8);
} >iram0_2_seg :iram0_2_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_3_end = ALIGN(0x8);
} >iram0_3_seg :iram0_3_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_4_end = ALIGN(0x8);
} >iram0_4_seg :iram0_4_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_5_end = ALIGN(0x8);
} >iram0_5_seg :iram0_5_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_6_end = ALIGN(0x8);
} >iram0_6_seg :iram0_6_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
_iram0_text_end = ABSOLUTE(.);
_image_rom_end = ABSOLUTE(.);
} >iram0_7_seg :iram0_7_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >iram0_7_seg :iram0_7_phdr
_image_text_end = .;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -1,16 +0,0 @@
# Kconfig - XTENSA board configuration
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 Cadence Design Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_HIFI_MINI_4SWIRQ
config SOC
string
default "hifi_mini_4swIrq"
config IRQ_OFFLOAD_INTNUM
default 1
endif

View file

@ -1,5 +0,0 @@
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_HIFI_MINI_4SWIRQ
bool "hifi_mini_4swIrq (hifi_mini core with 4 additional SW IRQs)"

View file

@ -1,369 +0,0 @@
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <linker/sections.h>
#include <linker/linker-defs.h>
#include <linker/linker-tool.h>
#define RAMABLE_REGION sram0_0_seg :sram0_0_phdr
#define ROMABLE_REGION srom1_seg :srom1_phdr
MEMORY
{
dram0_0_seg : org = 0x60000000, len = 0x20000
iram0_0_seg : org = 0x60020000, len = 0x2E0
iram0_1_seg : org = 0x600202E0, len = 0x4
iram0_2_seg : org = 0x600202E4, len = 0x1C
iram0_3_seg : org = 0x60020300, len = 0x4
iram0_4_seg : org = 0x60020304, len = 0x1C
iram0_5_seg : org = 0x60020320, len = 0x4
iram0_6_seg : org = 0x60020324, len = 0x1C
iram0_7_seg : org = 0x60020340, len = 0x1FCC0
#ifdef CONFIG_GEN_ISR_TABLES
IDT_LIST : org = 0x5fffe000, len = 0x2000
#endif
}
PHDRS
{
dram0_0_phdr PT_LOAD;
dram0_0_bss_phdr PT_LOAD;
iram0_0_phdr PT_LOAD;
iram0_1_phdr PT_LOAD;
iram0_2_phdr PT_LOAD;
iram0_3_phdr PT_LOAD;
iram0_4_phdr PT_LOAD;
iram0_5_phdr PT_LOAD;
iram0_6_phdr PT_LOAD;
iram0_7_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(CONFIG_KERNEL_ENTRY)
/* Memory boundary addresses: */
_memmap_mem_dram0_start = 0x60000000;
_memmap_mem_dram0_end = 0x60020000;
_memmap_mem_iram0_start = 0x60020000;
_memmap_mem_iram0_end = 0x60040000;
/* Memory segment boundary addresses: */
_memmap_seg_dram0_0_start = 0x60000000;
_memmap_seg_dram0_0_max = 0x60020000;
_memmap_seg_iram0_0_start = 0x60020000;
_memmap_seg_iram0_0_max = 0x600202e0;
_memmap_seg_iram0_1_start = 0x600202e0;
_memmap_seg_iram0_1_max = 0x600202e4;
_memmap_seg_iram0_2_start = 0x600202e4;
_memmap_seg_iram0_2_max = 0x60020300;
_memmap_seg_iram0_3_start = 0x60020300;
_memmap_seg_iram0_3_max = 0x60020304;
_memmap_seg_iram0_4_start = 0x60020304;
_memmap_seg_iram0_4_max = 0x60020320;
_memmap_seg_iram0_5_start = 0x60020320;
_memmap_seg_iram0_5_max = 0x60020324;
_memmap_seg_iram0_6_start = 0x60020324;
_memmap_seg_iram0_6_max = 0x60020340;
_memmap_seg_iram0_7_start = 0x60020340;
_memmap_seg_iram0_7_max = 0x60040000;
_rom_store_table = 0;
PROVIDE(_memmap_reset_vector = 0x60020000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00001000;
_memmap_cacheattr_wt_base = 0x00001000;
_memmap_cacheattr_bp_base = 0x00002000;
_memmap_cacheattr_unused_mask = 0xFFFF0FFF;
_memmap_cacheattr_wb_trapnull = 0x2222122F;
_memmap_cacheattr_wba_trapnull = 0x2222122F;
_memmap_cacheattr_wbna_trapnull = 0x2222122F;
_memmap_cacheattr_wt_trapnull = 0x2222122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFF1FFF;
_memmap_cacheattr_wt_strict = 0xFFFF1FFF;
_memmap_cacheattr_bp_strict = 0xFFFF2FFF;
_memmap_cacheattr_wb_allvalid = 0x22221222;
_memmap_cacheattr_wt_allvalid = 0x22221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
#include <linker/rel-sections.ld>
.dram0.rodata : ALIGN(4)
{
_dram0_rodata_start = ABSOLUTE(.);
_image_ram_start = ABSOLUTE(.);
*(.dram0.rodata)
*(.dram.rodata)
_dram0_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
#include <linker/common-rom.ld>
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
*(.rodata1)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
KEEP (*(.xt_except_table))
KEEP (*(.gcc_except_table))
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
KEEP (*(.eh_frame))
/* C++ constructor and destructor tables, properly ordered: */
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.literal : ALIGN(4)
{
_dram0_literal_start = ABSOLUTE(.);
*(.dram0.literal)
*(.dram.literal)
_dram0_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.ResetVector.literal : ALIGN(4)
{
_ResetVector_literal_start = ABSOLUTE(.);
*(.ResetVector.literal)
_ResetVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.dram0.data : ALIGN(4)
{
_dram0_data_start = ABSOLUTE(.);
*(.dram0.data)
*(.dram.data)
_dram0_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.sram.data : ALIGN(4)
{
_sram_data_start = ABSOLUTE(.);
*(.sram.data)
_sram_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.noinit : ALIGN(4)
{
*(.noinit)
*(.noinit.*)
} >dram0_0_seg :dram0_0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
KEEP(*(.gnu.linkonce.d.*personality*))
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
KEEP(*(.jcr))
_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
#include <linker/common-ram.ld>
.bss (NOLOAD) : ALIGN(8)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.dram0.bss)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
_end = ALIGN(0x8);
_image_ram_end = ABSOLUTE(.);
PROVIDE(end = ALIGN(0x8));
_stack_sentry = ALIGN(0x8);
_memmap_seg_dram0_0_end = ALIGN(0x8);
} >dram0_0_seg :dram0_0_bss_phdr
__stack = 0x60020000;
_heap_sentry = 0x60020000;
.ResetVector.text : ALIGN(4)
{
_image_rom_start = ABSOLUTE(.);
_ResetVector_text_start = ABSOLUTE(.);
KEEP (*(.ResetVector.text))
_ResetVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_0_end = ALIGN(0x8);
} >iram0_0_seg :iram0_0_phdr
.KernelExceptionVector.literal : ALIGN(4)
{
_KernelExceptionVector_literal_start = ABSOLUTE(.);
*(.KernelExceptionVector.literal)
_KernelExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_1_end = ALIGN(0x8);
} >iram0_1_seg :iram0_1_phdr
.KernelExceptionVector.text : ALIGN(4)
{
_KernelExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.KernelExceptionVector.text))
_KernelExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_2_end = ALIGN(0x8);
} >iram0_2_seg :iram0_2_phdr
.UserExceptionVector.literal : ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_3_end = ALIGN(0x8);
} >iram0_3_seg :iram0_3_phdr
.UserExceptionVector.text : ALIGN(4)
{
_UserExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.UserExceptionVector.text))
_UserExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_4_end = ALIGN(0x8);
} >iram0_4_seg :iram0_4_phdr
.DoubleExceptionVector.literal : ALIGN(4)
{
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
*(.DoubleExceptionVector.literal)
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
_memmap_seg_iram0_5_end = ALIGN(0x8);
} >iram0_5_seg :iram0_5_phdr
.DoubleExceptionVector.text : ALIGN(4)
{
_DoubleExceptionVector_text_start = ABSOLUTE(.);
KEEP (*(.DoubleExceptionVector.text))
_DoubleExceptionVector_text_end = ABSOLUTE(.);
_memmap_seg_iram0_6_end = ALIGN(0x8);
} >iram0_6_seg :iram0_6_phdr
.iram0.text : ALIGN(4)
{
_iram0_text_start = ABSOLUTE(.);
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
_iram0_text_end = ABSOLUTE(.);
_image_rom_end = ABSOLUTE(.);
} >iram0_7_seg :iram0_7_phdr
_image_text_start = ALIGN(4);
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
*(.entry.text)
*(.init.literal)
KEEP(*(.init))
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
KEEP(*(.fini))
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >iram0_7_seg :iram0_7_phdr
_image_text_end = .;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_ranges 0 : { *(.debug_ranges) }
.xtensa.info 0 : { *(.xtensa.info) }
.xt.insn 0 :
{
KEEP (*(.xt.insn))
KEEP (*(.gnu.linkonce.x.*))
}
.xt.prop 0 :
{
KEEP (*(.xt.prop))
KEEP (*(.xt.prop.*))
KEEP (*(.gnu.linkonce.prop.*))
}
.xt.lit 0 :
{
KEEP (*(.xt.lit))
KEEP (*(.xt.lit.*))
KEEP (*(.gnu.linkonce.p.*))
}
.debug.xt.callgraph 0 :
{
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
}
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
}

View file

@ -12,9 +12,6 @@ config SOC
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM
default 0 default 0
config XTENSA_ASM2
default y
# S1000 does not have MISC0. # S1000 does not have MISC0.
# Since EXCSAVE2 is unused by Zephyr, use it instead. # Since EXCSAVE2 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR config XTENSA_KERNEL_CPU_PTR_SR

View file

@ -13,9 +13,6 @@ config SOC
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM
default 7 default 7
config XTENSA_ASM2
default y
config LOG_BACKEND_XTENSA_SIM config LOG_BACKEND_XTENSA_SIM
default LOG default LOG