From 6fd6b7e50a671aee5b7d116c831dc902cbd55326 Mon Sep 17 00:00:00 2001 From: Andrew Boie Date: Tue, 13 Aug 2019 14:02:29 -0700 Subject: [PATCH] xtensa: remove legacy arch implementation We re-wrote the xtensa arch code, but never got around to purging the old implementation. Removed those boards which hadn't been moved to the new arch code. These were all xt-sim simulator targets and not real hardware. Fixes: #18138 Signed-off-by: Andrew Boie --- arch/Kconfig | 2 + arch/xtensa/Kconfig | 11 - arch/xtensa/core/CMakeLists.txt | 14 - arch/xtensa/core/irq_manage.c | 51 - arch/xtensa/core/swap.S | 93 - arch/xtensa/core/thread.c | 123 -- arch/xtensa/core/xt_zephyr.S | 386 ---- arch/xtensa/core/xtensa-asm2-util.S | 4 - arch/xtensa/core/xtensa-asm2.c | 8 - arch/xtensa/core/xtensa_context.S | 609 ------ arch/xtensa/core/xtensa_intr.c | 39 - arch/xtensa/core/xtensa_intr_asm.S | 118 -- arch/xtensa/core/xtensa_vectors.S | 1647 ----------------- arch/xtensa/include/kernel_arch_data.h | 2 - arch/xtensa/include/kernel_arch_func.h | 35 - arch/xtensa/include/xtensa_api.h | 8 - boards/xtensa/xt-sim/doc/index.rst | 12 +- boards/xtensa/xt-sim/xt-sim_D_108mini.yaml | 6 - .../xtensa/xt-sim/xt-sim_D_108mini_defconfig | 13 - boards/xtensa/xt-sim/xt-sim_D_212GP.yaml | 6 - boards/xtensa/xt-sim/xt-sim_D_212GP_defconfig | 13 - boards/xtensa/xt-sim/xt-sim_D_233L.yaml | 6 - boards/xtensa/xt-sim/xt-sim_D_233L_defconfig | 13 - .../xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM.yaml | 6 - .../xt-sim_XRC_FUSION_AON_ALL_LM_defconfig | 13 - boards/xtensa/xt-sim/xt-sim_hifi2_std.yaml | 6 - .../xtensa/xt-sim/xt-sim_hifi2_std_defconfig | 13 - boards/xtensa/xt-sim/xt-sim_hifi3_bd5.yaml | 6 - .../xtensa/xt-sim/xt-sim_hifi3_bd5_defconfig | 13 - drivers/timer/xtensa_sys_timer.c | 11 - include/arch/xtensa/arch.h | 6 +- soc/xtensa/D_108mini/Kconfig.defconfig | 16 - soc/xtensa/D_108mini/Kconfig.soc | 5 - soc/xtensa/D_108mini/linker.ld | 611 ------ soc/xtensa/D_212GP/Kconfig.defconfig | 16 - soc/xtensa/D_212GP/Kconfig.soc | 5 - soc/xtensa/D_212GP/linker.ld | 617 ------ soc/xtensa/D_233L/Kconfig.defconfig | 16 - soc/xtensa/D_233L/Kconfig.soc | 5 - soc/xtensa/D_233L/linker.ld | 519 ------ soc/xtensa/XRC_D2PM_5swIrq/Kconfig.defconfig | 16 - soc/xtensa/XRC_D2PM_5swIrq/Kconfig.soc | 5 - soc/xtensa/XRC_D2PM_5swIrq/linker.ld | 621 ------- .../XRC_FUSION_AON_ALL_LM/Kconfig.defconfig | 16 - soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.soc | 5 - soc/xtensa/XRC_FUSION_AON_ALL_LM/linker.ld | 450 ----- soc/xtensa/esp32/Kconfig.defconfig | 3 - soc/xtensa/hifi2_std/Kconfig.defconfig | 16 - soc/xtensa/hifi2_std/Kconfig.soc | 5 - soc/xtensa/hifi2_std/linker.ld | 621 ------- soc/xtensa/hifi3_bd5/Kconfig.defconfig | 16 - soc/xtensa/hifi3_bd5/Kconfig.soc | 5 - soc/xtensa/hifi3_bd5/linker.ld | 397 ---- soc/xtensa/hifi3_bd5_call0/Kconfig.defconfig | 16 - soc/xtensa/hifi3_bd5_call0/Kconfig.soc | 5 - soc/xtensa/hifi3_bd5_call0/linker.ld | 397 ---- soc/xtensa/hifi4_bd7/Kconfig.defconfig | 16 - soc/xtensa/hifi4_bd7/Kconfig.soc | 5 - soc/xtensa/hifi4_bd7/linker.ld | 444 ----- soc/xtensa/hifi_mini/Kconfig.defconfig | 16 - soc/xtensa/hifi_mini/Kconfig.soc | 5 - soc/xtensa/hifi_mini/linker.ld | 369 ---- soc/xtensa/hifi_mini_4swIrq/Kconfig.defconfig | 16 - soc/xtensa/hifi_mini_4swIrq/Kconfig.soc | 5 - soc/xtensa/hifi_mini_4swIrq/linker.ld | 369 ---- soc/xtensa/intel_s1000/Kconfig.defconfig | 3 - .../sample_controller/Kconfig.defconfig | 3 - 67 files changed, 5 insertions(+), 8943 deletions(-) delete mode 100644 arch/xtensa/core/irq_manage.c delete mode 100644 arch/xtensa/core/swap.S delete mode 100644 arch/xtensa/core/thread.c delete mode 100644 arch/xtensa/core/xt_zephyr.S delete mode 100644 arch/xtensa/core/xtensa_context.S delete mode 100644 arch/xtensa/core/xtensa_intr.c delete mode 100644 arch/xtensa/core/xtensa_intr_asm.S delete mode 100644 arch/xtensa/core/xtensa_vectors.S delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_108mini.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_108mini_defconfig delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_212GP.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_212GP_defconfig delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_233L.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_D_233L_defconfig delete mode 100644 boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM_defconfig delete mode 100644 boards/xtensa/xt-sim/xt-sim_hifi2_std.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_hifi2_std_defconfig delete mode 100644 boards/xtensa/xt-sim/xt-sim_hifi3_bd5.yaml delete mode 100644 boards/xtensa/xt-sim/xt-sim_hifi3_bd5_defconfig delete mode 100644 soc/xtensa/D_108mini/Kconfig.defconfig delete mode 100644 soc/xtensa/D_108mini/Kconfig.soc delete mode 100644 soc/xtensa/D_108mini/linker.ld delete mode 100644 soc/xtensa/D_212GP/Kconfig.defconfig delete mode 100644 soc/xtensa/D_212GP/Kconfig.soc delete mode 100644 soc/xtensa/D_212GP/linker.ld delete mode 100644 soc/xtensa/D_233L/Kconfig.defconfig delete mode 100644 soc/xtensa/D_233L/Kconfig.soc delete mode 100644 soc/xtensa/D_233L/linker.ld delete mode 100644 soc/xtensa/XRC_D2PM_5swIrq/Kconfig.defconfig delete mode 100644 soc/xtensa/XRC_D2PM_5swIrq/Kconfig.soc delete mode 100644 soc/xtensa/XRC_D2PM_5swIrq/linker.ld delete mode 100644 soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.defconfig delete mode 100644 soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.soc delete mode 100644 soc/xtensa/XRC_FUSION_AON_ALL_LM/linker.ld delete mode 100644 soc/xtensa/hifi2_std/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi2_std/Kconfig.soc delete mode 100644 soc/xtensa/hifi2_std/linker.ld delete mode 100644 soc/xtensa/hifi3_bd5/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi3_bd5/Kconfig.soc delete mode 100644 soc/xtensa/hifi3_bd5/linker.ld delete mode 100644 soc/xtensa/hifi3_bd5_call0/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi3_bd5_call0/Kconfig.soc delete mode 100644 soc/xtensa/hifi3_bd5_call0/linker.ld delete mode 100644 soc/xtensa/hifi4_bd7/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi4_bd7/Kconfig.soc delete mode 100644 soc/xtensa/hifi4_bd7/linker.ld delete mode 100644 soc/xtensa/hifi_mini/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi_mini/Kconfig.soc delete mode 100644 soc/xtensa/hifi_mini/linker.ld delete mode 100644 soc/xtensa/hifi_mini_4swIrq/Kconfig.defconfig delete mode 100644 soc/xtensa/hifi_mini_4swIrq/Kconfig.soc delete mode 100644 soc/xtensa/hifi_mini_4swIrq/linker.ld diff --git a/arch/Kconfig b/arch/Kconfig index 08400bb0469..213f473c036 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -48,6 +48,8 @@ config RISCV config XTENSA bool "Xtensa architecture" select HAS_DTS + select USE_SWITCH + select USE_SWITCH_SUPPORTED config ARCH_POSIX bool "POSIX (native) architecture" diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 77cfbef977d..86d4acd403d 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -31,17 +31,6 @@ config XTENSA_OMIT_HIGH_INTERRUPTS code. Default is "n" for legacy compatibility. Consider changing to "y" in the future. -config XTENSA_ASM2 - bool "New-style Xtensa context switch & interrupt layer" - select USE_SWITCH - select USE_SWITCH_SUPPORTED - help - This selects a new implementation of context switching and - interrupt handling. Advantages are a much lower interrupt - overhead and smaller code size, and this scheme is required - for SMP. Assumes/requires hardware that implements the - register window extension, however. - endmenu config ARCH diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index c364d3f8272..62fcc2445dc 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -5,24 +5,10 @@ zephyr_sources( cpu_idle.c fatal.c window_vectors.S - ) - -zephyr_sources_ifdef(CONFIG_XTENSA_ASM2 xtensa-asm2-util.S xtensa-asm2.c ) -zephyr_sources_ifndef(CONFIG_XTENSA_ASM2 - xtensa_intr.c - irq_manage.c - swap.S - thread.c - xtensa_context.S - xtensa_intr_asm.S - xtensa_vectors.S - xt_zephyr.S - ) - zephyr_sources_ifndef(CONFIG_ATOMIC_OPERATIONS_C atomic.S) zephyr_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S diff --git a/arch/xtensa/core/irq_manage.c b/arch/xtensa/core/irq_manage.c deleted file mode 100644 index 3c8c791a639..00000000000 --- a/arch/xtensa/core/irq_manage.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -/* - * @internal - * - * @brief Set an interrupt's priority - * - * The priority is verified if ASSERT_ON is enabled. - * - * The priority is verified if ASSERT_ON is enabled. The maximum number of - * priority levels is a little complex, as there are some hardware priority - * levels which are reserved: three for various types of exceptions, and - * possibly one additional to support zero latency interrupts. - * - * Valid values are from 1 to 6. Interrupts of priority 1 are not masked when - * interrupts are locked system-wide, so care must be taken when using them. - * ISR installed with priority 0 interrupts cannot make kernel calls. - * - * @return N/A - */ - -void z_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags) -{ - __ASSERT(prio < XCHAL_EXCM_LEVEL + 1, - "invalid priority %d! values must be less than %d\n", - prio, XCHAL_EXCM_LEVEL + 1); - /* TODO: Write code to set priority if this is ever possible on - * Xtensa - */ -} - -#ifdef CONFIG_DYNAMIC_INTERRUPTS -int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(void *parameter), void *parameter, - u32_t flags) -{ - ARG_UNUSED(flags); - ARG_UNUSED(priority); - - z_isr_install(irq, routine, parameter); - return irq; -} -#endif /* CONFIG_DYNAMIC_INTERRUPTS */ diff --git a/arch/xtensa/core/swap.S b/arch/xtensa/core/swap.S deleted file mode 100644 index e59230cdd0b..00000000000 --- a/arch/xtensa/core/swap.S +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief kernel swapper code for Xtensa - * - * This module implements the __swap() routine for the Xtensa architecture. - */ - -#include -#include -#include - - .extern _kernel -/* unsigned int __swap (unsigned int basepri); */ - .globl __swap - .type __swap,@function - .align 4 -__swap: -#ifdef __XTENSA_CALL0_ABI__ - addi sp, sp, -XT_SOL_FRMSZ -#else - entry sp, XT_SOL_FRMSZ -#endif - s32i a0, sp, XT_SOL_pc - s32i a2, sp, XT_SOL_ps -#ifdef __XTENSA_CALL0_ABI__ - s32i a12, sp, XT_SOL_a12 /* save callee-saved registers */ - s32i a13, sp, XT_SOL_a13 - s32i a14, sp, XT_SOL_a14 - s32i a15, sp, XT_SOL_a15 -#else - /* Spill register windows. Calling xthal_window_spill() causes extra - * spills and reloads, so we will set things up to call the _nw version - * instead to save cycles. - */ - /* spills a4-a7 if needed */ - movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) - and a2, a2, a6 /* clear WOE, INTLEVEL */ - addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */ - wsr a2, PS - rsync - call0 xthal_window_spill_nw - l32i a2, sp, XT_SOL_ps /* restore PS */ - addi a2, a2, XCHAL_EXCM_LEVEL - wsr a2, PS -#endif -#if XCHAL_CP_NUM > 0 - /* Save coprocessor callee-saved state (if any). At this point CPENABLE - * should still reflect which CPs were in use (enabled). - */ - call0 _xt_coproc_savecs -#endif - movi a2, _kernel - movi a3, 0 - l32i a4, a2, KERNEL_OFFSET(current) /* a4 := _kernel->current */ - - s32i a3, sp, XT_SOL_exit /* 0 to flag as solicited frame */ - s32i sp, a4, THREAD_OFFSET(sp) /* current->arch.topOfStack := sp */ - /* - * Set __swap()'s default return code to -EAGAIN. This eliminates the - * need for the timeout code to set it itself. - */ - movi a3, -11 /* a3 := -EAGAIN. TODO: Use a macro here insted of 11 */ - s32i a3, a4, THREAD_OFFSET(retval) /* current->arch.retval := -EAGAIN */ - -#if XCHAL_CP_NUM > 0 - /* Clear CPENABLE, also in task's co-processor state save area. */ - movi a3, 0 - /* a4 = _kernel->current */ - wsr a3, CPENABLE - s16i a3, a4, THREAD_OFFSET(cpEnable) /* clear saved cpenable */ -#endif - -#ifdef CONFIG_TRACING - /* Register the context switch */ -#ifdef __XTENSA_CALL0_ABI__ - call0 z_sys_trace_thread_switched_in -#else - call4 z_sys_trace_thread_switched_in -#endif -#endif - /* _thread := _kernel.ready_q.cache */ - l32i a3, a2, KERNEL_OFFSET(ready_q_cache) - /* - * Swap threads if any is to be swapped in. - */ - call0 _zxt_dispatch /* (_kernel@a2, _thread@a3) */ - /* Never reaches here. */ - diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c deleted file mode 100644 index 5a7a3075d6d..00000000000 --- a/arch/xtensa/core/thread.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifdef CONFIG_DEBUG -#include -#endif -#include -#include -#include -#include - -extern void z_xt_user_exit(void); - -/* - * @brief Initialize a new thread - * - * Any coprocessor context data is put at the lower address of the stack. An - * initial context, to be "restored" by __return_from_coop(), is put at - * the other end of the stack, and thus reusable by the stack when not - * needed anymore. - * - * The initial context is a basic stack frame that contains arguments for - * z_thread_entry() return address, that points at z_thread_entry() - * and status register. - * - * is currently unused. - * - * @param thread pointer to k_thread memory - * @param pStackmem the pointer to aligned stack memory - * @param stackSize the stack size in bytes - * @param pEntry thread entry point routine - * @param p1 first param to entry point - * @param p2 second param to entry point - * @param p3 third param to entry point - * @param priority thread priority - * @param options is unused (saved for future expansion) - * - * @return N/A - */ - -void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, - size_t stackSize, k_thread_entry_t pEntry, - void *p1, void *p2, void *p3, - int priority, unsigned int options) -{ - char *pStack = Z_THREAD_STACK_BUFFER(stack); - - /* Align stack end to maximum alignment requirement. */ - char *stackEnd = (char *)ROUND_DOWN(pStack + stackSize, 16); -#if XCHAL_CP_NUM > 0 - u32_t *cpSA; - char *cpStack; -#endif - - z_new_thread_init(thread, pStack, stackSize, priority, options); - -#ifdef CONFIG_DEBUG - printk("\nstackPtr = %p, stackSize = %d\n", pStack, stackSize); - printk("stackEnd = %p\n", stackEnd); -#endif -#if XCHAL_CP_NUM > 0 - /* Ensure CP state descriptor is correctly initialized */ - cpStack = thread->arch.preempCoprocReg.cpStack; /* short hand alias */ - /* Set to zero to avoid bad surprises */ - (void)memset(cpStack, 0, XT_CP_ASA); - /* Coprocessor's stack is allocated just after the k_thread */ - cpSA = (u32_t *)(thread->arch.preempCoprocReg.cpStack + XT_CP_ASA); - /* Coprocessor's save area alignment is at leat 16 bytes */ - *cpSA = ROUND_UP(cpSA + 1, - (XCHAL_TOTAL_SA_ALIGN < 16 ? 16 : XCHAL_TOTAL_SA_ALIGN)); -#ifdef CONFIG_DEBUG - printk("cpStack = %p\n", thread->arch.preempCoprocReg.cpStack); - printk("cpAsa = %p\n", - *(void **)(thread->arch.preempCoprocReg.cpStack + XT_CP_ASA)); -#endif -#endif - /* Thread's first frame alignment is granted as both operands are - * aligned - */ - XtExcFrame *pInitCtx = - (XtExcFrame *)(stackEnd - (XT_XTRA_SIZE - XT_CP_SIZE)); -#ifdef CONFIG_DEBUG - printk("pInitCtx = %p\n", pInitCtx); -#endif - /* Explicitly initialize certain saved registers */ - - /* task entrypoint */ - pInitCtx->pc = (u32_t)z_thread_entry; - - /* physical top of stack frame */ - pInitCtx->a1 = (u32_t)pInitCtx + XT_STK_FRMSZ; - - /* user exception exit dispatcher */ - pInitCtx->exit = (u32_t)z_xt_user_exit; - - /* Set initial PS to int level 0, EXCM disabled, user mode. - * Also set entry point argument arg. - */ -#ifdef __XTENSA_CALL0_ABI__ - pInitCtx->a2 = (u32_t)pEntry; - pInitCtx->a3 = (u32_t)p1; - pInitCtx->a4 = (u32_t)p2; - pInitCtx->a5 = (u32_t)p3; - pInitCtx->ps = PS_UM | PS_EXCM; -#else - /* For windowed ABI set also WOE and CALLINC - * (pretend task is 'call4') - */ - pInitCtx->a6 = (u32_t)pEntry; - pInitCtx->a7 = (u32_t)p1; - pInitCtx->a8 = (u32_t)p2; - pInitCtx->a9 = (u32_t)p3; - pInitCtx->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); -#endif - thread->callee_saved.topOfStack = pInitCtx; - thread->arch.flags = 0; - /* initial values in all other registers/k_thread entries are - * irrelevant - */ -} - diff --git a/arch/xtensa/core/xt_zephyr.S b/arch/xtensa/core/xt_zephyr.S deleted file mode 100644 index 0bd59451a52..00000000000 --- a/arch/xtensa/core/xt_zephyr.S +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - - .extern _interrupt_stack - .extern _kernel -#ifdef CONFIG_SYS_CLOCK_EXISTS - .extern timer_int_handler -#endif - .set _interrupt_stack_top, _interrupt_stack + CONFIG_ISR_STACK_SIZE - -/* - * _zxt_dispatch(_kernel_t *_kernel, _thread_t *_thread) - * At this point, the a2 register contains the '&_kernel' and the - * thread to be swapped in (&_thread) is in a3. - */ - .text - .globl _zxt_dispatch - .type _zxt_dispatch,@function - .align 4 -_zxt_dispatch: - /* Updated current thread: _kernel.current := _kernel.ready_q.cache */ - s32i a3, a2, KERNEL_OFFSET(current) /* _kernel.current := _thread */ - l32i sp, a3, THREAD_OFFSET(sp) /* sp := _thread->topOfStack; */ - - /* Determine the type of stack frame. */ - l32i a2, sp, XT_STK_exit /* exit dispatcher or solicited flag */ - bnez a2, .L_frxt_dispatch_stk - -.L_frxt_dispatch_sol: - /* Solicited stack frame. Restore retval from z_swap */ - l32i a2, a3, THREAD_OFFSET(retval) - l32i a3, sp, XT_SOL_ps - -#ifdef __XTENSA_CALL0_ABI__ - l32i a12, sp, XT_SOL_a12 - l32i a13, sp, XT_SOL_a13 - l32i a14, sp, XT_SOL_a14 - l32i a15, sp, XT_SOL_a15 -#endif - l32i a0, sp, XT_SOL_pc -#if XCHAL_CP_NUM > 0 - /* Ensure wsr.CPENABLE is complete (should be, it was cleared on - * entry). - */ - rsync -#endif - /* As soons as PS is restored, interrupts can happen. No need to sync - * PS. - */ - wsr a3, PS -#ifdef __XTENSA_CALL0_ABI__ - addi sp, sp, XT_SOL_FRMSZ - ret -#else - retw -#endif - -.L_frxt_dispatch_stk: - -#if XCHAL_CP_NUM > 0 - /* Restore CPENABLE from task's co-processor save area. */ - l16ui a3, a3, THREAD_OFFSET(cpEnable) /* a3 := cp_state->cpenable */ - wsr a3, CPENABLE -#endif -#ifdef CONFIG_STACK_SENTINEL -#ifdef __XTENSA_CALL0_ABI__ - call0 z_check_stack_sentinel -#else - call4 z_check_stack_sentinel -#endif -#endif - /* - * Interrupt stack frame. - * Restore full context and return to exit dispatcher. - */ - call0 _xt_context_restore - - /* In Call0 ABI, restore callee-saved regs (A12, A13 already - * restored). - */ -#ifdef __XTENSA_CALL0_ABI__ - l32i a14, sp, XT_STK_a14 - l32i a15, sp, XT_STK_a15 -#endif - -#if XCHAL_CP_NUM > 0 - /* Ensure wsr.CPENABLE has completed. */ - rsync -#endif - - /* - * Must return via the exit dispatcher corresponding to the entrypoint - * from which this was called. Interruptee's A0, A1, PS, PC are - * restored and the interrupt stack frame is deallocated in the exit - * dispatcher. - */ - l32i a0, sp, XT_STK_exit - ret - -/* - * _zxt_int_enter - * void _zxt_int_enter(void) - * - * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for - * freeRTOS. Saves the rest of the interrupt context (not already saved). - * May only be called from assembly code by the 'call0' instruction, with - * interrupts disabled. - * See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. - */ - .globl _zxt_int_enter - .type _zxt_int_enter,@function - .align 4 -_zxt_int_enter: - - /* Save a12-13 in the stack frame as required by _xt_context_save. */ - s32i a12, a1, XT_STK_a12 - s32i a13, a1, XT_STK_a13 - - /* Save return address in a safe place (free a0). */ - mov a12, a0 - - /* Save the rest of the interrupted context (preserves A12-13). */ - call0 _xt_context_save - - /* - * Save interrupted task's SP in TCB only if not nesting. Manage - * nesting directly rather than call the generic IntEnter() (in - * windowed ABI we can't call a C function here anyway because PS.EXCM - * is still set). - */ - movi a2, _kernel /* a2 := _kernel */ - l32i a3, a2, KERNEL_OFFSET(nested) /* a3 := _kernel->nested */ - addi a3, a3, 1 /* increment nesting count */ - s32i a3, a2, KERNEL_OFFSET(nested) /* save nesting count */ - bnei a3, 1, .Lnested /* !=0 before incr, so nested */ - - l32i a3, a2, KERNEL_OFFSET(current)/* a3 := _kernel->current */ - s32i a1, a3, THREAD_OFFSET(sp) /* save SP to Current top of stack */ - movi a1, _interrupt_stack_top /* a1 = top of intr stack */ -.Lnested: -1: - mov a0, a12 /* restore return addr and return */ - ret - -/* - * _zxt_int_exit - * void _zxt_int_exit(void) - * - * Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for - * Zephyr. If required, calls vPortYieldFromInt() to perform task context - * switching, restore the (possibly) new task's context, and return to the exit - * dispatcher saved in the task's stack frame at XT_STK_EXIT. May only be - * called from assembly code by the 'call0' instruction. Does not return to - * caller. See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h. - - */ - .globl _zxt_int_exit - .type _zxt_int_exit,@function - .align 4 -_zxt_int_exit: - - rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */ - movi a2, _kernel - l32i a3, a2, KERNEL_OFFSET(nested) /* _kernel->nested */ - addi a3, a3, -1 /* decrement nesting count */ - s32i a3, a2, KERNEL_OFFSET(nested) /* save nesting count */ - bnez a3, .Lnesting /* !=0 after decr so still nested */ - - /* - * When using call0 ABI callee-saved registers a12-15 need to be saved - * before enabling preemption. They were already saved by - * _zxt_int_enter(). - */ -#ifdef __XTENSA_CALL0_ABI__ - s32i a14, a1, XT_STK_a14 - s32i a15, a1, XT_STK_a15 -#endif - -#if XCHAL_CP_NUM > 0 - l32i a3, a2, KERNEL_OFFSET(current) /* _thread := _kernel->current */ - rsr a5, CPENABLE - s16i a5, a3, THREAD_OFFSET(cpEnable) /* cp_state->cpenable = CPENABLE */ - movi a3, 0 - wsr a3, CPENABLE /* disable all co-processors */ -#endif - l32i a3, a2, KERNEL_OFFSET(current) /* _thread := _kernel.current */ - /* _thread := _kernel.ready_q.cache */ - l32i a3, a2, KERNEL_OFFSET(ready_q_cache) -.noReschedule: - /* - * Swap threads if any is to be swapped in. - */ - call0 _zxt_dispatch /* (_kernel@a2, _thread@a3) */ - /* Never returns here. */ - -.Lnesting: - /* - * We come here only if there was no context switch, that is if this - * is a nested interrupt, or the interrupted task was not preempted. - * In either case there's no need to load the SP. - */ - - /* Restore full context from interrupt stack frame */ - call0 _xt_context_restore - - /* - * Must return via the exit dispatcher corresponding to the entrypoint - * from which this was called. Interruptee's A0, A1, PS, PC are - * restored and the interrupt stack frame is deallocated in the exit - * dispatcher. - */ - l32i a0, sp, XT_STK_exit - ret - -/* - * _zxt_timer_int - * void _zxt_timer_int(void) - * - * Implements Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function. Called - * every timer interrupt. Manages the tick timer and calls - * xPortSysTickHandler() every tick. See the detailed description of the - * XT_RTOS_ENTER macro in xtensa_rtos.h. Callable from C. Implemented in - * assembly code for performance. - * - */ - .globl _zxt_timer_int - .type _zxt_timer_int,@function - .align 4 -_zxt_timer_int: - - /* - * Xtensa timers work by comparing a cycle counter with a preset value. - * Once the match occurs an interrupt is generated, and the handler has - * to set a new cycle count into the comparator. To avoid clock drift - * due to interrupt latency, the new cycle count is computed from the - * old, not the time the interrupt was serviced. However if a timer - * interrupt is ever serviced more than one tick late, it is necessary - * to process multiple ticks until the new cycle count is in the - * future, otherwise the next timer interrupt would not occur until - * after the cycle counter had wrapped (2^32 cycles later). - * - * do { - * ticks++; - * old_ccompare = read_ccompare_i(); - * write_ccompare_i( old_ccompare + divisor ); - * service one tick; - * diff = read_ccount() - old_ccompare; - * } while ( diff > divisor ); - */ - - ENTRY(16) -.L_xt_timer_int_catchup: -#ifdef CONFIG_SYS_CLOCK_EXISTS - -#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) - /* Update the timer comparator for the next tick. */ -#ifdef XT_CLOCK_FREQ - movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */ -#else - movi a3, _xt_tick_divisor - l32i a2, a3, 0 /* a2 = comparator increment */ -#endif - rsr a3, XT_CCOMPARE /* a3 = old comparator value */ - add a4, a3, a2 /* a4 = new comparator value */ - wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */ - esync -#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */ - - -#ifdef __XTENSA_CALL0_ABI__ - /* Preserve a2 and a3 across C calls. */ - s32i a2, sp, 4 - s32i a3, sp, 8 - /* TODO: movi a2, _xt_interrupt_table */ - movi a3, timer_int_handler - /* TODO: l32i a2, a2, 0 */ - callx0 a3 - /* Restore a2 and a3. */ - l32i a2, sp, 4 - l32i a3, sp, 8 -#else - /* TODO: movi a6, _xt_interrupt_table */ - movi a7, timer_int_handler - /* TODO: l32i a6, a6, 0 */ - callx4 a7 -#endif - -#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) - /* Check if we need to process more ticks to catch up. */ - esync /* ensure comparator update complete */ - rsr a4, CCOUNT /* a4 = cycle count */ - sub a4, a4, a3 /* diff = ccount - old comparator */ - blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */ -#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */ - -#endif - - RET(16) - -/* - * _zxt_tick_timer_init - * void _zxt_tick_timer_init(void) - * - * Initialize timer and timer interrupt handler (z_xt_tick_divisor_init() has - * already been been called). - * Callable from C (obeys ABI conventions on entry). - * - */ - .globl _zxt_tick_timer_init - .type _zxt_tick_timer_init,@function - .align 4 -_zxt_tick_timer_init: - - ENTRY(48) -#ifdef CONFIG_SYS_CLOCK_EXISTS -#if USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) - - /* Set up the periodic tick timer (assume enough time to complete - * init). - */ -#ifdef XT_CLOCK_FREQ - movi a3, XT_TICK_DIVISOR -#else - movi a2, _xt_tick_divisor - l32i a3, a2, 0 -#endif - rsr a2, CCOUNT /* current cycle count */ - add a2, a2, a3 /* time of first timer interrupt */ - wsr a2, XT_CCOMPARE /* set the comparator */ - - /* - Enable the timer interrupt at the device level. Don't write directly - to the INTENABLE register because it may be virtualized. - */ -#ifdef __XTENSA_CALL0_ABI__ - movi a2, XT_TIMER_INTEN - call0 z_xt_ints_on -#else - movi a6, XT_TIMER_INTEN - call4 z_xt_ints_on -#endif - -#endif -#endif /* USE_INTERNAL_TIMER || (EXTERNAL_TIMER_IRQ < 0) */ - RET(48) - -/* - * _zxt_task_coproc_state - * void _zxt_task_coproc_state(void) - * - * Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function. - * - * May only be called when a task is running, not within an interrupt handler - * (returns 0 in that case). - * May only be called from assembly code by the 'call0' instruction. - * Does NOT obey ABI conventions. - * Returns in A15 a pointer to the base of the co-processor state save area - * for the current task. - * See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. - * - */ -#if XCHAL_CP_NUM > 0 - - .globl _zxt_task_coproc_state - .type _zxt_task_coproc_state,@function - .align 4 -_zxt_task_coproc_state: - movi a2, _kernel - l32i a15, a2, KERNEL_OFFSET(nested) - bnez a15, 1f - l32i a2, a2, KERNEL_OFFSET(current) - beqz a2, 1f - addi a15, a2, THREAD_OFFSET(cpStack) - ret - -1: movi a15, 0 -2: ret -#endif /* XCHAL_CP_NUM > 0 */ - diff --git a/arch/xtensa/core/xtensa-asm2-util.S b/arch/xtensa/core/xtensa-asm2-util.S index c68e2830350..1ee56a33c43 100644 --- a/arch/xtensa/core/xtensa-asm2-util.S +++ b/arch/xtensa/core/xtensa-asm2-util.S @@ -228,8 +228,6 @@ xtensa_switch: _switch_restore_pc: retw -#ifdef CONFIG_XTENSA_ASM2 - /* Define our entry handler to load the struct kernel_t from the * MISC0 special register, and to find the nest and irq_stack values * at the precomputed offsets. @@ -320,5 +318,3 @@ _DoubleExceptionVector: j 1b .popsection #endif - -#endif /* CONFIG_XTENSA_ASM2 */ diff --git a/arch/xtensa/core/xtensa-asm2.c b/arch/xtensa/core/xtensa-asm2.c index 0036d7a4178..c0c60862083 100644 --- a/arch/xtensa/core/xtensa-asm2.c +++ b/arch/xtensa/core/xtensa-asm2.c @@ -53,11 +53,6 @@ void *xtensa_init_stack(int *stack_top, return &bsa[-9]; } -/* This is a kernel hook, just a wrapper around other APIs. Build - * only if we're using asm2 as the core OS interface and not just as - * utilities/testables. - */ -#ifdef CONFIG_XTENSA_ASM2 void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz, k_thread_entry_t entry, void *p1, void *p2, void *p3, int prio, unsigned int opts) @@ -73,9 +68,7 @@ void z_new_thread(struct k_thread *thread, k_thread_stack_t *stack, size_t sz, thread->switch_handle = xtensa_init_stack((void *)top, entry, p1, p2, p3); } -#endif -#ifdef CONFIG_XTENSA_ASM2 void z_irq_spurious(void *arg) { int irqs, ie; @@ -88,7 +81,6 @@ void z_irq_spurious(void *arg) (void *)irqs, (void *)ie); z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } -#endif void z_xtensa_dump_stack(const z_arch_esf_t *stack) { diff --git a/arch/xtensa/core/xtensa_context.S b/arch/xtensa/core/xtensa_context.S deleted file mode 100644 index b5bb625c3f6..00000000000 --- a/arch/xtensa/core/xtensa_context.S +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES - * - * Low-level Call0 functions for handling generic context save and restore of - * registers not specifically addressed by the interrupt vectors and handlers. - * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). - * Except for the calls to RTOS functions, this code is generic to Xtensa. - * - * Note that in Call0 ABI, interrupt handlers are expected to preserve the - * callee-save regs (A12-A15), which is always the case if the handlers are - * coded in C. However A12, A13 are made available as scratch registers for - * interrupt dispatch code, so are presumed saved anyway, and are always - * restored even in Call0 ABI. Only A14, A15 are truly handled as callee-save - * regs. - * - * Because Xtensa is a configurable architecture, this port supports all user - * generated configurations (except restrictions stated in the release notes). - * This is accomplished by conditional compilation using macros and functions - * defined in the Xtensa HAL (hardware adaptation layer) for your - * configuration. Only the processor state included in your configuration is - * saved and restored, including any processor state added by user - * configuration options or TIE. - */ - -/* Warn nicely if this file gets named with a lowercase .s instead of .S: */ -#define NOERROR # -NOERROR: .error "C preprocessor needed for this file: make sure its filename\ - ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option." - - -#include "xtensa_rtos.h" - -#ifdef XT_USE_OVLY -#include -#endif - - .text - -/* - * _xt_context_save - * - * !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! - * - * Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in - * the interrupt stack frame defined in xtensa_rtos.h. Its counterpart is - * _xt_context_restore (which also restores A12, A13). - * - * Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame. - * This function preserves A12 & A13 in order to provide the caller with 2 - * scratch regs that need not be saved over the call to this function. The - * choice of which 2 regs to provide is governed by xthal_window_spill_nw and - * xthal_save_extra_nw, to avoid moving data more than necessary. Caller can - * assign regs accordingly. - * - * Entry Conditions: - * A0 = Return address in caller. - * A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * Original A12, A13 have already been saved in the interrupt stack frame. - * Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the - * point of interruption. - * If windowed ABI, PS.EXCM = 1 (exceptions disabled). - * - * Exit conditions: - * A0 = Return address in caller. - * A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * A12, A13 as at entry (preserved). - * If windowed ABI, PS.EXCM = 1 (exceptions disabled). - */ - - .global _xt_context_save - .type _xt_context_save,@function - .align 4 -_xt_context_save: - - s32i a2, sp, XT_STK_a2 - s32i a3, sp, XT_STK_a3 - s32i a4, sp, XT_STK_a4 - s32i a5, sp, XT_STK_a5 - s32i a6, sp, XT_STK_a6 - s32i a7, sp, XT_STK_a7 - s32i a8, sp, XT_STK_a8 - s32i a9, sp, XT_STK_a9 - s32i a10, sp, XT_STK_a10 - s32i a11, sp, XT_STK_a11 - - /* Call0 ABI callee-saved regs a12-15 do not need to be saved here. a12-13 - * are the caller's responsibility so it can use them as scratch. So only - * need to save a14-a15 here for Windowed ABI (not Call0). - */ - #ifndef __XTENSA_CALL0_ABI__ - s32i a14, sp, XT_STK_a14 - s32i a15, sp, XT_STK_a15 - #endif - - rsr a3, SAR - s32i a3, sp, XT_STK_sar - - #if XCHAL_HAVE_LOOPS - rsr a3, LBEG - s32i a3, sp, XT_STK_lbeg - rsr a3, LEND - s32i a3, sp, XT_STK_lend - rsr a3, LCOUNT - s32i a3, sp, XT_STK_lcount - #endif - - #if XT_USE_SWPRI - /* Save virtual priority mask */ - movi a3, _xt_vpri_mask - l32i a3, a3, 0 - s32i a3, sp, XT_STK_VPRI - #endif - - #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) - mov a9, a0 /* preserve ret addr */ - #endif - - #ifndef __XTENSA_CALL0_ABI__ - /* To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15. - * Need to save a9,12,13 temporarily (in frame temps) and recover - * originals. Interrupts need to be disabled below XCHAL_EXCM_LEVEL and - * window overflow and underflow exceptions disabled (assured by PS.EXCM == - * 1). - */ - s32i a12, sp, XT_STK_tmp0 /* temp. save stuff in stack frame */ - s32i a13, sp, XT_STK_tmp1 - s32i a9, sp, XT_STK_tmp2 - - /* Save the overlay state if we are supporting overlays. Since we just - * saved three registers, we can conveniently use them here. Note that as - * of now, overlays only work for windowed calling ABI. - */ - #ifdef XT_USE_OVLY - l32i a9, sp, XT_STK_PC /* recover saved PC */ - _xt_overlay_get_state a9, a12, a13 - s32i a9, sp, XT_STK_OVLY /* save overlay state */ - #endif - - l32i a12, sp, XT_STK_a12 /* recover original a9,12,13 */ - l32i a13, sp, XT_STK_a13 - l32i a9, sp, XT_STK_a9 - addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */ - call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */ - addi sp, sp, -XT_STK_FRMSZ - l32i a12, sp, XT_STK_tmp0 /* recover stuff from stack frame */ - l32i a13, sp, XT_STK_tmp1 - l32i a9, sp, XT_STK_tmp2 - #endif - - #if XCHAL_EXTRA_SA_SIZE > 0 - /* NOTE: Normally the xthal_save_extra_nw macro only affects address - * registers a2-a5. It is theoretically possible for Xtensa processor - * designers to write TIE that causes more address registers to be - * affected, but it is generally unlikely. If that ever happens, more - * registers need to be saved/restored around this macro invocation. Here - * we assume a9,12,13 are preserved. Future Xtensa tools releases might - * limit the regs that can be affected. - */ - addi a2, sp, XT_STK_EXTRA /* where to save it */ - # if XCHAL_EXTRA_SA_ALIGN > 16 - movi a3, -XCHAL_EXTRA_SA_ALIGN - and a2, a2, a3 /* align dynamically >16 bytes */ - # endif - call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */ - #endif - - #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__) - mov a0, a9 /* retrieve ret addr */ - #endif - - ret - -/*_xt_context_restore - * - * !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !! - * - * Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0 - * ABI, A14, A15 which are preserved by all interrupt handlers) from an - * interrupt stack frame defined in xtensa_rtos.h. Its counterpart is - * _xt_context_save (whose caller saved A12, A13). - * - * Caller is responsible to restore PC, PS, A0, A1 (SP). - * - * Entry Conditions: - * A0 = Return address in caller. - * A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * - * Exit conditions: - * A0 = Return address in caller. - * A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * Other processor state except PC, PS, A0, A1 (SP), is as at the point - * of interruption. - */ - - .global _xt_context_restore - .type _xt_context_restore,@function - .align 4 -_xt_context_restore: - - #if XCHAL_EXTRA_SA_SIZE > 0 - /* NOTE: Normally the xthal_restore_extra_nw macro only affects address - * registers a2-a5. It is theoretically possible for Xtensa processor - * designers to write TIE that causes more address registers to be - * affected, but it is generally unlikely. If that ever happens, more - * registers need to be saved/restored around this macro invocation. Here - * we only assume a13 is preserved. Future Xtensa tools releases might - * limit the regs that can be affected. - */ - mov a13, a0 /* preserve ret addr */ - addi a2, sp, XT_STK_EXTRA /* where to find it */ - # if XCHAL_EXTRA_SA_ALIGN > 16 - movi a3, -XCHAL_EXTRA_SA_ALIGN - and a2, a2, a3 /* align dynamically >16 bytes */ - # endif - call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */ - mov a0, a13 /* retrieve ret addr */ - #endif - - #if XCHAL_HAVE_LOOPS - l32i a2, sp, XT_STK_lbeg - l32i a3, sp, XT_STK_lend - wsr a2, LBEG - l32i a2, sp, XT_STK_lcount - wsr a3, LEND - wsr a2, LCOUNT - #endif - - #ifdef XT_USE_OVLY - /* If we are using overlays, this is a good spot to check if we need to - * restore an overlay for the incoming task. Here we have a bunch of - * registers to spare. Note that this step is going to use a few bytes of - * storage below SP (SP-20 to SP-32) if an overlay is going to be - * restored. - */ - l32i a2, sp, XT_STK_pc /* retrieve PC */ - l32i a3, sp, XT_STK_ps /* retrieve PS */ - l32i a4, sp, XT_STK_ovly /* retrieve overlay state */ - l32i a5, sp, XT_STK_a1 /* retrieve stack ptr */ - _xt_overlay_check_map a2, a3, a4, a5, a6 - s32i a2, sp, XT_STK_pc /* save updated PC */ - s32i a3, sp, XT_STK_ps /* save updated PS */ - #endif - - #ifdef XT_USE_SWPRI - /* Restore virtual interrupt priority and interrupt enable */ - movi a3, _xt_intdata - l32i a4, a3, 0 /* a4 = _xt_intenable */ - l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */ - and a4, a4, a5 - wsr a4, INTENABLE /* update INTENABLE */ - s32i a5, a3, 4 /* restore _xt_vpri_mask */ - #endif - - l32i a3, sp, XT_STK_sar - l32i a2, sp, XT_STK_a2 - wsr a3, SAR - l32i a3, sp, XT_STK_a3 - l32i a4, sp, XT_STK_a4 - l32i a5, sp, XT_STK_a5 - l32i a6, sp, XT_STK_a6 - l32i a7, sp, XT_STK_a7 - l32i a8, sp, XT_STK_a8 - l32i a9, sp, XT_STK_a9 - l32i a10, sp, XT_STK_a10 - l32i a11, sp, XT_STK_a11 - - /* - * Call0 ABI callee-saved regs a12-15 do not need to be restored here. - * However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), - * so need to be restored anyway, despite being callee-saved in Call0. - */ - l32i a12, sp, XT_STK_a12 - l32i a13, sp, XT_STK_a13 - #ifndef __XTENSA_CALL0_ABI__ - l32i a14, sp, XT_STK_a14 - l32i a15, sp, XT_STK_a15 - #endif - - ret - - -/* z_xt_coproc_init - * - * Initializes global co-processor management data, setting all co-processors - * to "unowned". Leaves CPENABLE as it found it (does NOT clear it). - * - * Called during initialization of the RTOS, before any threads run. - * - * This may be called from normal Xtensa single-threaded application code which - * might use co-processors. The Xtensa run-time initialization enables all - * co-processors. They must remain enabled here, else a co-processor exception - * might occur outside of a thread, which the exception handler doesn't expect. - * - * Entry Conditions: - * Xtensa single-threaded run-time environment is in effect. - * No thread is yet running. - * - * Exit conditions: - * None. - * - * Obeys ABI conventions per prototype: - * void z_xt_coproc_init(void) - */ - -#if XCHAL_CP_NUM > 0 - - .global z_xt_coproc_init - .type z_xt_coproc_init,@function - .align 4 -z_xt_coproc_init: - ENTRY0 - - /* Initialize thread co-processor ownerships to 0 (unowned). */ - movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ - addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */ - movi a4, 0 /* a4 = 0 (unowned) */ -1: s32i a4, a2, 0 - addi a2, a2, 4 - bltu a2, a3, 1b - - RET0 - -#endif - - -/* _xt_coproc_release - * - * Releases any and all co-processors owned by a given thread. The thread is - * identified by it's co-processor state save area defined in xtensa_context.h - * - * Must be called before a thread's co-proc save area is deleted to avoid - * memory corruption when the exception handler tries to save the state. - * May be called when a thread terminates or completes but does not delete - * the co-proc save area, to avoid the exception handler having to save the - * thread's co-proc state before another thread can use it (optimization). - * - * Entry Conditions: - * A2 = Pointer to base of co-processor state save area. - * - * Exit conditions: - * None. - * - * Obeys ABI conventions per prototype: - * void _xt_coproc_release(void * coproc_sa_base) - */ - -#if XCHAL_CP_NUM > 0 - - .global _xt_coproc_release - .type _xt_coproc_release,@function - .align 4 -_xt_coproc_release: - ENTRY0 /* a2 = base of save area */ - - movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ - addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ - movi a5, 0 /* a5 = 0 (unowned) */ - - rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ - -1: l32i a7, a3, 0 /* a7 = owner at a3 */ - bne a2, a7, 2f /* if (coproc_sa_base == owner) */ - s32i a5, a3, 0 /* owner = unowned */ -2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ - bltu a3, a4, 1b /* repeat until end of array */ - -3: wsr a6, PS /* restore interrupts */ - - RET0 - -#endif - - -/* _xt_coproc_savecs - * - * If there is a current thread and it has a coprocessor state save area, then - * save all callee-saved state into this area. This function is called from the - * solicited context switch handler. It calls a system-specific function to get - * the coprocessor save area base address. - * - * Entry conditions: - * - The thread being switched out is still the current thread. - * - CPENABLE state reflects which coprocessors are active. - * - Registers have been saved/spilled already. - * - * Exit conditions: - * - All necessary CP callee-saved state has been saved. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - */ - -#if XCHAL_CP_NUM > 0 - - .extern _xt_coproc_sa_offset /* external reference */ - - .global _xt_coproc_savecs - .type _xt_coproc_savecs,@function - .align 4 -_xt_coproc_savecs: - - /* At entry, CPENABLE should be showing which CPs are enabled. */ - - rsr a2, CPENABLE /* a2 = which CPs are enabled */ - beqz a2, .Ldone /* quick exit if none */ - mov a14, a0 /* save return address */ - call0 XT_RTOS_CP_STATE /* get address of CP save area */ - mov a0, a14 /* restore return address */ - beqz a15, .Ldone /* if none then nothing to do */ - s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ - movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone: - ret -#endif - - -/* - * _xt_coproc_restorecs - * - * Restore any callee-saved coprocessor state for the incoming thread. - * This function is called from coprocessor exception handling, when giving - * ownership to a thread that solicited a context switch earlier. It calls a - * system-specific function to get the coprocessor save area base address. - * - * Entry conditions: - * - The incoming thread is set as the current thread. - * - CPENABLE is set up correctly for all required coprocessors. - * - a2 = mask of coprocessors to be restored. - * - * Exit conditions: - * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - */ - -#if XCHAL_CP_NUM > 0 - - .global _xt_coproc_restorecs - .type _xt_coproc_restorecs,@function - .align 4 -_xt_coproc_restorecs: - - mov a14, a0 /* save return address */ - call0 XT_RTOS_CP_STATE /* get address of CP save area */ - mov a0, a14 /* restore return address */ - beqz a15, .Ldone2 /* if none then nothing to do */ - l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ - xor a3, a3, a2 /* clear the ones being restored */ - s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */ - movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 \ - select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone2: - ret - -#endif - diff --git a/arch/xtensa/core/xtensa_intr.c b/arch/xtensa/core/xtensa_intr.c deleted file mode 100644 index 121a8d869b9..00000000000 --- a/arch/xtensa/core/xtensa_intr.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Xtensa-specific interrupt and exception functions for RTOS ports. - * Also see xtensa_intr_asm.S. - */ - -#include - -#include -#include "xtensa_rtos.h" -#include "xtensa_api.h" -#include -#include - -#if XCHAL_HAVE_EXCEPTIONS -static void unhandled_exception_trampoline(XtExcFrame *frame) -{ - FatalErrorHandler(); - CODE_UNREACHABLE; -} - -typedef void (*xt_exc_handler)(XtExcFrame *); - -xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM] __aligned(4) = { - [0 ... (XCHAL_EXCCAUSE_NUM - 1)] = unhandled_exception_trampoline -}; -#endif - -#if defined(CONFIG_SW_ISR_TABLE) && defined(XCHAL_HAVE_INTERRUPTS) -void z_irq_spurious(void *arg) -{ - ReservedInterruptHandler((unsigned int)arg); - CODE_UNREACHABLE; -} -#endif diff --git a/arch/xtensa/core/xtensa_intr_asm.S b/arch/xtensa/core/xtensa_intr_asm.S deleted file mode 100644 index 9099bac3083..00000000000 --- a/arch/xtensa/core/xtensa_intr_asm.S +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/****************************************************************************** - Xtensa interrupt handling data and assembly routines. - Also see xtensa_intr.c and xtensa_vectors.S. -******************************************************************************/ - -#include -#include -#include "xtensa_rtos.h" -#include "xtensa_context.h" - -#if XCHAL_HAVE_INTERRUPTS - -/* -------------------------------------------------------------------------------- - INTENABLE virtualization information. -------------------------------------------------------------------------------- -*/ - - .data - .global _xt_intdata - .align 8 -_xt_intdata: - .global _xt_intenable - .type _xt_intenable,@object - .size _xt_intenable,4 - .global _xt_vpri_mask - .type _xt_vpri_mask,@object - .size _xt_vpri_mask,4 - -_xt_intenable: .word 0 /* Virtual INTENABLE */ -_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */ - - -#endif /* XCHAL_HAVE_INTERRUPTS */ - - -/* -------------------------------------------------------------------------------- - unsigned int z_xt_ints_on ( unsigned int mask ) - - Enables a set of interrupts. Does not simply set INTENABLE directly, but - computes it as a function of the current virtual priority. - Can be called from interrupt handlers. -------------------------------------------------------------------------------- -*/ - - .text - .align 4 - .global z_xt_ints_on - .type z_xt_ints_on,@function - -z_xt_ints_on: - - ENTRY0 -#if XCHAL_HAVE_INTERRUPTS - movi a3, 0 - movi a4, _xt_intdata - xsr a3, INTENABLE /* Disables all interrupts */ - rsync - l32i a3, a4, 0 /* a3 = _xt_intenable */ - l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ - or a5, a3, a2 /* a5 = _xt_intenable | mask */ - s32i a5, a4, 0 /* _xt_intenable |= mask */ - and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ - wsr a5, INTENABLE /* Reenable interrupts */ - mov a2, a3 /* Previous mask */ -#else - movi a2, 0 /* Return zero */ -#endif - RET0 - - .size z_xt_ints_on, . - z_xt_ints_on - - -/* -------------------------------------------------------------------------------- - unsigned int z_xt_ints_off ( unsigned int mask ) - - Disables a set of interrupts. Does not simply set INTENABLE directly, - but computes it as a function of the current virtual priority. - Can be called from interrupt handlers. -------------------------------------------------------------------------------- -*/ - - .text - .align 4 - .global z_xt_ints_off - .type z_xt_ints_off,@function - -z_xt_ints_off: - - ENTRY0 -#if XCHAL_HAVE_INTERRUPTS - movi a3, 0 - movi a4, _xt_intdata - xsr a3, INTENABLE /* Disables all interrupts */ - rsync - l32i a3, a4, 0 /* a3 = _xt_intenable */ - l32i a6, a4, 4 /* a6 = _xt_vpri_mask */ - or a5, a3, a2 /* a5 = _xt_intenable | mask */ - xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */ - s32i a5, a4, 0 /* _xt_intenable &= ~mask */ - and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ - wsr a5, INTENABLE /* Reenable interrupts */ - mov a2, a3 /* Previous mask */ -#else - movi a2, 0 /* return zero */ -#endif - RET0 - - .size z_xt_ints_off, . - z_xt_ints_off - - diff --git a/arch/xtensa/core/xtensa_vectors.S b/arch/xtensa/core/xtensa_vectors.S deleted file mode 100644 index 73d447f8101..00000000000 --- a/arch/xtensa/core/xtensa_vectors.S +++ /dev/null @@ -1,1647 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/* XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS - * - * FIXME: A lot of this is not applicable to Zephyr, remove. In particular, - * we do not support installing interrupt or exception handlers at runtime. - * - * Xtensa low level exception and interrupt vectors and handlers for an RTOS. - * - * Interrupt handlers and user exception handlers support interaction with the - * RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and after - * user's specific interrupt handlers. These macros are defined in - * xtensa_.h to call suitable functions in a specific RTOS. - * - * Users can install application-specific interrupt handlers for low and medium - * level interrupts, by calling _xt_set_interrupt_handler(). These handlers can - * be written in C, and must obey C calling convention. The handler table is - * indexed by the interrupt number. Each handler may be provided with an - * argument. - * - * Note that the system timer interrupt is handled specially, and is dispatched - * to the RTOS-specific handler. This timer cannot be hooked by application - * code. - * - * Optional hooks are also provided to install a handler per level at run-time, - * made available by compiling this source file with '-DXT_INTEXC_HOOKS' - * (useful for automated testing). - * - * NOTE: This file is a template that usually needs to be modified to handle - * application specific interrupts. Search USER_EDIT for helpful comments on - * where to insert handlers and how to write them. - * - * Users can also install application-specific exception handlers in the same - * way, by calling _xt_set_exception_handler(). One handler slot is provided - * for each exception type. Note that some exceptions are handled by the - * porting layer itself, and cannot be taken over by application code in this - * manner. These are the alloca, syscall, and coprocessor exceptions. - * - * The exception handlers can be written in C, and must follow C calling - * convention. Each handler is passed a pointer to an exception frame as its - * single argument. The exception frame is created on the stack, and holds the - * saved context of the thread that took the exception. If the handler returns, - * the context will be restored and the instruction that caused the exception - * will be retried. If the handler makes any changes to the saved state in the - * exception frame, the changes will be applied when restoring the context. - * - * Because Xtensa is a configurable architecture, this port supports all user - * generated configurations (except restrictions stated in the release notes). - * This is accomplished by conditional compilation using macros and functions - * defined in the Xtensa HAL (hardware adaptation layer) for your - * configuration. Only the relevant parts of this file will be included in your - * RTOS build. For example, this file provides interrupt vector templates for - * all types and all priority levels, but only the ones in your configuration - * are built. - * - * NOTES on the use of 'call0' for long jumps instead of 'j': - * - * 1. This file should be assembled with the -mlongcalls option to xt-xcc. - * - * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to - * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the - * distance from the call to the destination. The linker then relaxes - * it back to 'call0 dest' if it determines that dest is within range. - * This allows more flexibility in locating code without the performance - * overhead of the 'l32r' literal data load in cases where the destination - * is in range of 'call0'. There is an additional benefit in that 'call0' - * has a longer range than 'j' due to the target being word-aligned, so - * the 'l32r' sequence is less likely needed. - * - * 3. The use of 'call0' with -mlongcalls requires that register a0 not be - * live at the time of the call, which is always the case for a function - * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. - * - * 4. This use of 'call0' is independent of the C function call ABI. - */ - -#include -#include "xtensa_rtos.h" - -#define GEN_MED_INTERRUPT(l) \ - (XCHAL_NUM_INTLEVELS >= (l) && \ - XCHAL_DEBUGLEVEL != (l) && \ - XCHAL_EXCM_LEVEL >= (l)) - -#define GEN_HIGH_INTERRUPT(l) \ - (XCHAL_NUM_INTLEVELS >= (l) && \ - XCHAL_DEBUGLEVEL != (l) && \ - (XCHAL_EXCM_LEVEL < (l) && !defined(CONFIG_XTENSA_OMIT_HIGH_INTERRUPTS))) - -/* - * Defines used to access _xtos_interrupt_table. - */ -/** - * Zephyr has its own SW interrupt service routines table. - * Xtensa's table is made an alias of it. - **/ -#define _xt_interrupt_table _sw_isr_table -#define XIE_ARG 0 -#define XIE_HANDLER 4 -#define XIE_SIZE 8 - -/* Macro extract_msb - return the input with only the highest bit set. - * - * Input : "ain" - Input value, clobbered. - * Output : "aout" - Output value, has only one bit set, MSB of "ain". - * - * The two arguments must be different AR registers. - */ - - .macro extract_msb aout ain -1: - addi \aout, \ain, -1 /* aout = ain - 1 */ - and \ain, \ain, \aout /* ain = ain & aout */ - bnez \ain, 1b /* repeat until ain == 0 */ - addi \aout, \aout, 1 /* return aout + 1 */ - .endm - -/* Macro dispatch_c_isr - dispatch interrupts to user ISRs. - * This will dispatch to user handlers (if any) that are registered in the - * XTOS dispatch table (_xtos_interrupt_table). These handlers would have - * been registered by calling _xtos_set_interrupt_handler(). There is one - * exception - the timer interrupt used by the OS will not be dispatched - * to a user handler - this must be handled by the caller of this macro. - * - * Level triggered and software interrupts are automatically deasserted by - * this code. - * - * ASSUMPTIONS: - * -- PS.INTLEVEL is set to "level" at entry - * -- PS.EXCM = 0, C calling enabled - * - * NOTE: For CALL0 ABI, a12-a15 have not yet been saved. - * - * NOTE: This macro will use registers a0 and a2-a6. The arguments are: - * level -- interrupt level - * mask -- interrupt bitmask for this level - */ - .extern _kernel - .extern z_sys_power_save_idle_exit - - .macro dispatch_c_isr level mask - - /* Get mask of pending, enabled interrupts at this level into a2. */ - -.L_xt_user_int_&level&: - rsr a2, INTENABLE - rsr a3, INTERRUPT - movi a4, \mask - and a2, a2, a3 - and a2, a2, a4 - beqz a2, 9f /* nothing to do */ - - /* This bit of code provides a nice debug backtrace in the debugger. - It does take a few more instructions, so undef XT_DEBUG_BACKTRACE - if you want to save the cycles. - */ - #if XT_DEBUG_BACKTRACE - #ifndef __XTENSA_CALL0_ABI__ - rsr a0, EPC_1 + \level - 1 /* return address */ - movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ - or a0, a0, a4 /* set top 2 bits */ - addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ - #endif - #endif - -#ifdef CONFIG_TRACING - /* - * Register the interrupt. - * We just saved all registers. - */ -#ifdef __XTENSA_CALL0_ABI__ - call0 z_sys_trace_isr_enter -#else - call4 z_sys_trace_isr_enter -#endif -#endif - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a4, _xt_intexc_hooks - l32i a4, a4, \level << 2 - beqz a4, 2f - #ifdef __XTENSA_CALL0_ABI__ - callx0 a4 - beqz a2, 9f - #else - mov a6, a2 - callx4 a4 - beqz a6, 9f - mov a2, a6 - #endif -2: - #endif - -#ifdef CONFIG_SYS_POWER_MANAGEMENT - movi a3, _kernel -#ifdef __XTENSA_CALL0_ABI__ - mov a12, a2 - l32i a2, a3, _kernel_offset_to_idle - beqz a2, 10f - xor a4, a2, a2 - s32i a4, a3, _kernel_offset_to_idle - call0 z_sys_power_save_idle_exit - mov a2, a12 -#else - l32i a6, a3, _kernel_offset_to_idle - beqz a6, 10f - xor a4, a6, a6 - s32i a4, a3, _kernel_offset_to_idle - call4 z_sys_power_save_idle_exit -#endif /* __XTENSA_CALL0_ABI__ */ -10: -#endif /* CONFIG_SYS_POWER_MANAGEMENT */ - - /* Now look up in the dispatch table and call user ISR if any. */ - /* If multiple bits are set then MSB has highest priority. */ - - extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ - - #ifdef XT_USE_SWPRI - /* Enable all interrupts at this level that are numerically highe - * than the one we just selected, since they are treated as higher - * priority. - * */ - movi a3, \mask /* a3 = all interrupts at this level */ - add a2, a4, a4 /* a2 = a4 << 1 */ - addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ - and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ - movi a3, _xt_intdata - l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ - neg a2, a2 - addi a2, a2, -1 /* a2 = mask to apply */ - and a5, a6, a2 /* mask off all bits <= a4 bit */ - s32i a5, a3, 4 /* update _xt_vpri_mask */ - rsr a3, INTENABLE - and a3, a3, a2 /* mask off all bits <= a4 bit */ - wsr a3, INTENABLE - rsil a3, \level - 1 /* lower interrupt level by 1 */ - #endif - - movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ - wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ - beq a3, a4, 7f /* if timer interrupt then skip table */ - - find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ - - movi a4, _xt_interrupt_table - addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ - l32i a4, a3, XIE_HANDLER /* a4 = handler address */ - #ifdef __XTENSA_CALL0_ABI__ - mov a12, a6 /* save in callee-saved reg */ - l32i a2, a3, XIE_ARG /* a2 = handler arg */ - callx0 a4 /* call handler */ - mov a2, a12 - #else - mov a2, a6 /* save in windowed reg */ - l32i a6, a3, XIE_ARG /* a6 = handler arg */ - callx4 a4 /* call handler */ - #endif - - #ifdef XT_USE_SWPRI - j 8f - #else - j .L_xt_user_int_&level& /* check for more interrupts */ - #endif - -7: - - .ifeq XT_TIMER_INTPRI - \level -.L_xt_user_int_timer_&level&: - /* - * Interrupt handler for the RTOS tick timer if at this level. - * We'll be reading the interrupt state again after this call - * so no need to preserve any registers except a6 (vpri_mask). - */ - - #ifdef __XTENSA_CALL0_ABI__ - mov a12, a6 - call0 XT_RTOS_TIMER_INT - mov a2, a12 - #else - mov a2, a6 - call4 XT_RTOS_TIMER_INT - #endif - .endif - - #ifdef XT_USE_SWPRI - j 8f - #else - j .L_xt_user_int_&level& /* check for more interrupts */ - #endif - - #ifdef XT_USE_SWPRI -8: - /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE - * from virtual _xt_intenable which _could_ have changed during - * interrupt processing. - */ - movi a3, _xt_intdata - l32i a4, a3, 0 /* a4 = _xt_intenable */ - s32i a2, a3, 4 /* update _xt_vpri_mask */ - and a4, a4, a2 /* a4 = masked intenable */ - wsr a4, INTENABLE /* update INTENABLE */ - #endif - -9: - /* done */ - - .endm - - -/* Panic handler. - * - * Should be reached by call0 (preferable) or jump only. If call0, a0 says - * where from. If on simulator, display panic message and abort, else loop - * indefinitely. - */ - - .text - .global _xt_panic - .type _xt_panic,@function - .align 4 - -_xt_panic: - #ifdef XT_SIMULATOR - addi a4, a0, -3 /* point to call0 */ - movi a3, _xt_panic_message - movi a2, SYS_log_msg - simcall - movi a2, SYS_gdb_abort - simcall - #else - rsil a2, XCHAL_EXCM_LEVEL /* disable all low & med ints */ -1: j 1b /* loop infinitely */ - #endif - - .section .rodata, "a" - .align 4 - -_xt_panic_message: - .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n" - - -/* Hooks to dynamically install handlers for exceptions and interrupts. Allows - * automated regression frameworks to install handlers per test. Consists of - * an array of function pointers indexed by interrupt level, with index 0 - * containing the entry for user exceptions. Initialized with all 0s, meaning - * no handler is installed at each level. See comment in xtensa_rtos.h for - * more details. - */ - - #ifdef XT_INTEXC_HOOKS - .data - .global _xt_intexc_hooks - .type _xt_intexc_hooks,@object - .align 4 - -_xt_intexc_hooks: - .fill XT_INTEXC_HOOK_NUM, 4, 0 - #endif - - -/* EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS (except - * window exception vectors). - * - * Each vector goes at a predetermined location according to the Xtensa - * hardware configuration, which is ensured by its placement in a special - * section known to the Xtensa linker support package (LSP). It performs the - * minimum necessary before jumping to the handler in the .text section. - * - * The corresponding handler goes in the normal .text section. It sets up the - * appropriate stack frame, saves a few vector-specific registers and calls - * XT_RTOS_INT_ENTER to save the rest of the interrupted context and enter the - * RTOS, then sets up a C environment. It then calls the user's interrupt - * handler code (which may be coded in C) and finally calls XT_RTOS_INT_EXIT to - * transfer control to the RTOS for scheduling. - * - * While XT_RTOS_INT_EXIT does not return directly to the interruptee, - * eventually the RTOS scheduler will want to dispatch the interrupted task or - * handler. The scheduler will return to the exit point that was saved in the - * interrupt stack frame at XT_STK_EXIT. - */ - -/* - * Debug Exception. - */ - -#if XCHAL_HAVE_DEBUG - - .begin literal_prefix .DebugExceptionVector - .section .DebugExceptionVector.text, "ax" - .global _DebugExceptionVector - .align 4 - -_DebugExceptionVector: - - #ifdef XT_SIMULATOR - /* In the simulator, let the debugger (if any) handle the debug - * exception, or simply stop the simulation: - */ - wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL /* save a2 where sim expects it */ - movi a2, SYS_gdb_enter_sktloop - simcall /* have ISS handle debug exc. */ - #elif 0 /* change condition to 1 to use the HAL minimal debug handler */ - wsr a3, EXCSAVE+XCHAL_DEBUGLEVEL - movi a3, xthal_debugexc_defhndlr_nw /* use default debug handler */ - jx a3 - #else - wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */ - call0 _xt_panic /* does not return */ - rfi XCHAL_DEBUGLEVEL /* make a0 point here not later */ - #endif - - .end literal_prefix - -#endif - -/* Double Exception. - * - * Double exceptions are not a normal occurrence. They indicate a bug of some - * kind. - */ - -#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR - - .begin literal_prefix .DoubleExceptionVector - .section .DoubleExceptionVector.text, "ax" - .global _DoubleExceptionVector - .align 4 - -_DoubleExceptionVector: - - #if XCHAL_HAVE_DEBUG - break 1, 4 /* unhandled double exception */ - #endif - call0 _xt_panic /* does not return */ - rfde /* make a0 point here not later */ - - .end literal_prefix - -#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ - -/* - * Kernel Exception (including Level 1 Interrupt from kernel mode). - */ - - .begin literal_prefix .KernelExceptionVector - .section .KernelExceptionVector.text, "ax" - .global _KernelExceptionVector - .align 4 - -_KernelExceptionVector: - - wsr a0, EXCSAVE_1 /* preserve a0 */ - call0 _xt_kernel_exc /* kernel exception handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .align 4 - -_xt_kernel_exc: - #if XCHAL_HAVE_DEBUG - break 1, 0 /* unhandled kernel exception */ - #endif - call0 _xt_panic /* does not return */ - rfe /* make a0 point here not there */ - - -/* User Exception (including Level 1 Interrupt from user mode). */ - - .begin literal_prefix .UserExceptionVector - .section .UserExceptionVector.text, "ax" - .global _UserExceptionVector - .type _UserExceptionVector,@function - .align 4 - -_UserExceptionVector: - - wsr a0, EXCSAVE_1 /* preserve a0 */ - call0 _xt_user_exc /* user exception handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - -/* Insert some waypoints for jumping beyond the signed 8-bit range of - * conditional branch instructions, so the conditional branchces to specific - * exception handlers are not taken in the mainline. Saves some cycles in the - * mainline. - */ - .text - - #if XCHAL_HAVE_WINDOWED - .align 4 -_xt_to_alloca_exc: - call0 _xt_alloca_exc /* in window vectors section */ - /* never returns here - call0 is used as a jump (see note at top) */ - #endif - - .align 4 -_xt_to_syscall_exc: - call0 _xt_syscall_exc - /* never returns here - call0 is used as a jump (see note at top) */ - - #if XCHAL_CP_NUM > 0 - .align 4 -_xt_to_coproc_exc: - call0 _xt_coproc_exc - /* never returns here - call0 is used as a jump (see note at top) */ - #endif - - -/* - * User exception handler. - */ - - .type _xt_user_exc,@function - .align 4 - -_xt_user_exc: - - /* If level 1 interrupt then jump to the dispatcher */ - rsr a0, EXCCAUSE - beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1 - - /* Handle any coprocessor exceptions. Rely on the fact that exception - * numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. - */ - #if XCHAL_CP_NUM > 0 - bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc - #endif - - /* Handle alloca and syscall exceptions */ - #if XCHAL_HAVE_WINDOWED - beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc - #endif - beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc - - /* Handle all other exceptions. All can have user-defined handlers. */ - /* NOTE: we'll stay on the user stack for exception handling. */ - - /* Allocate exception frame and save minimal context. */ - mov a0, sp - addi sp, sp, -XT_STK_FRMSZ - s32i a0, sp, XT_STK_a1 - #if XCHAL_HAVE_WINDOWED - s32e a0, sp, -12 /* for debug backtrace */ - #endif - rsr a0, PS /* save interruptee's PS */ - s32i a0, sp, XT_STK_ps - rsr a0, EPC_1 /* save interruptee's PC */ - s32i a0, sp, XT_STK_pc - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ - s32i a0, sp, XT_STK_a0 - #if XCHAL_HAVE_WINDOWED - s32e a0, sp, -16 /* for debug backtrace */ - #endif - s32i a12, sp, XT_STK_a12 /* _xt_context_save requires A12- */ - s32i a13, sp, XT_STK_a13 /* A13 to have already been saved */ - call0 _xt_context_save - - /* Save exc cause and vaddr into exception frame */ - rsr a0, EXCCAUSE - s32i a0, sp, XT_STK_exccause - rsr a0, EXCVADDR - s32i a0, sp, XT_STK_excvaddr - - /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ - #ifdef __XTENSA_CALL0_ABI__ - movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM - #else - movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE - #endif - wsr a0, PS - - #ifdef XT_DEBUG_BACKTRACE - #ifndef __XTENSA_CALL0_ABI__ - rsr a0, EPC_1 /* return address for debug backtrace */ - /* constant with top 2 bits set (call size) */ - movi a5, 0xC0000000 - rsync /* wait for WSR.PS to complete */ - or a0, a0, a5 /* set top 2 bits */ - addx2 a0, a5, a0 /* clear top bit, simulating call4 size */ - #else - rsync /* wait for WSR.PS to complete */ - #endif - #endif - - rsr a2, EXCCAUSE /* recover exc cause */ - - #ifdef XT_INTEXC_HOOKS - /* Call exception hook to pre-handle exceptions (if installed). - * Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default - * handling). - */ - movi a4, _xt_intexc_hooks - l32i a4, a4, 0 /* user exception hook index 0 */ - beqz a4, 1f -.Ln_xt_user_exc_call_hook: - #ifdef __XTENSA_CALL0_ABI__ - callx0 a4 - beqi a2, -1, .L_xt_user_done - #else - mov a6, a2 - callx4 a4 - beqi a6, -1, .L_xt_user_done - mov a2, a6 - #endif -1: - #endif - - rsr a2, EXCCAUSE /* recover exc cause */ - movi a3, _xt_exception_table - addx4 a4, a2, a3 /* a4 = address of exception table entry */ - l32i a4, a4, 0 /* a4 = handler address */ - #ifdef __XTENSA_CALL0_ABI__ - mov a2, sp /* a2 = pointer to exc frame */ - callx0 a4 /* call handler */ - #else - mov a6, sp /* a6 = pointer to exc frame */ - callx4 a4 /* call handler */ - #endif - -.L_xt_user_done: - - /* Restore context and return */ - call0 _xt_context_restore - l32i a0, sp, XT_STK_ps /* retrieve interruptee's PS */ - wsr a0, PS - l32i a0, sp, XT_STK_pc /* retrieve interruptee's PC */ - wsr a0, EPC_1 - l32i a0, sp, XT_STK_a0 /* retrieve interruptee's A0 */ - l32i sp, sp, XT_STK_a1 /* remove exception frame */ - rsync /* ensure PS and EPC written */ - rfe /* PS.EXCM is cleared */ - - -/* - * Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT - * on entry and used to return to a thread or interrupted interrupt handler. - */ - - .global z_xt_user_exit - .type z_xt_user_exit,@function - .align 4 -z_xt_user_exit: - l32i a0, sp, XT_STK_ps /* retrieve interruptee's PS */ - wsr a0, PS - l32i a0, sp, XT_STK_pc /* retrieve interruptee's PC */ - wsr a0, EPC_1 - l32i a0, sp, XT_STK_a0 /* retrieve interruptee's A0 */ - l32i sp, sp, XT_STK_a1 /* remove interrupt stack frame */ - rsync /* ensure PS and EPC written */ - rfe /* PS.EXCM is cleared */ - - -/* Syscall Exception Handler (jumped to from User Exception Handler). - * - * Syscall 0 is required to spill the register windows (no-op in Call 0 ABI). - * Only syscall 0 is handled here. Other syscalls return -1 to caller in a2. - */ - - .text - .type _xt_syscall_exc,@function - .align 4 -_xt_syscall_exc: - #ifdef __XTENSA_CALL0_ABI__ - /* Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI. - * Use a minimal stack frame (16B) to save A2 & A3 for scratch. - * PS.EXCM could be cleared here, but unlikely to improve worst-case - * latency. - */ - addi sp, sp, -16 - s32i a2, sp, 8 - s32i a3, sp, 12 - #else /* Windowed ABI */ - /* Save necessary context and spill the register windows. PS.EXCM is - * still set and must remain set until after the spill. Reuse context - * save function though it saves more than necessary. For this reason, - * a full interrupt stack frame is allocated. - */ - addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ - s32i a12, sp, XT_STK_a12 /* _xt_context_save requires A12- */ - s32i a13, sp, XT_STK_a13 /* A13 to have already been saved */ - call0 _xt_context_save - #endif - - /* Grab the interruptee's PC and skip over the 'syscall' instruction. - * If it's at the end of a zero-overhead loop and it's not on the last - * iteration, decrement loop counter and skip to beginning of loop. - */ - rsr a2, EPC_1 /* a2 = PC of 'syscall' */ - addi a3, a2, 3 /* ++PC */ - #if XCHAL_HAVE_LOOPS - rsr a0, LEND /* if (PC == LEND */ - bne a3, a0, 1f - rsr a0, LCOUNT /* && LCOUNT != 0) */ - beqz a0, 1f /* { */ - addi a0, a0, -1 /* --LCOUNT */ - rsr a3, LBEG /* PC = LBEG */ - wsr a0, LCOUNT /* } */ - #endif -1: wsr a3, EPC_1 /* update PC */ - - /* Restore interruptee's context and return from exception. */ - #ifdef __XTENSA_CALL0_ABI__ - l32i a2, sp, 8 - l32i a3, sp, 12 - addi sp, sp, 16 - #else - call0 _xt_context_restore - addi sp, sp, XT_STK_FRMSZ - #endif - movi a0, -1 - movnez a2, a0, a2 /* return -1 if not syscall 0 */ - rsr a0, EXCSAVE_1 - rfe - -/* - * Co-Processor Exception Handler (jumped to from User Exception Handler). - * - * These exceptions are generated by co-processor instructions, which are only - * allowed in thread code (not in interrupts or kernel code). This restriction - * is deliberately imposed to reduce the burden of state-save/restore in - * interrupts. - */ -#if XCHAL_CP_NUM > 0 - - .section .rodata, "a" - -/* Offset to CP n save area in thread's CP save area. */ - .global _xt_coproc_sa_offset - .type _xt_coproc_sa_offset,@object - .align 16 /* minimize crossing cache boundaries */ -_xt_coproc_sa_offset: - .word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA - .word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA - -/* Bitmask for CP n's CPENABLE bit. */ - .type _xt_coproc_mask,@object - .align 16,,8 /* try to keep it all in one cache line */ - .set i, 0 -_xt_coproc_mask: - .rept XCHAL_CP_MAX - .long (i<<16) | (1< XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS - * - * High priority interrupts are by definition those with priorities greater - * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority - * interrupts cannot interact with the RTOS, that is they must save all regs - * they use and not call any RTOS function. - * - * A further restriction imposed by the Xtensa windowed architecture is that - * high priority interrupts must not modify the stack area even logically - * "above" the top of the interrupted stack (they need to provide their own - * stack or static save area). - * - * Cadence Design Systems recommends high priority interrupt handlers be coded - * in assembly and used for purposes requiring very short service times. - * - * Here are templates for high priority (level 2+) interrupt vectors. They - * assume only one interrupt per level to avoid the burden of identifying which - * interrupts at this level are pending and enabled. This allows for minimum - * latency and avoids having to save/restore a2 in addition to a0. If more than - * one interrupt per high priority level is configured, this burden is on the - * handler which in any case must provide a way to save and restore registers - * it uses without touching the interrupted stack. - * - * Each vector goes at a predetermined location according to the Xtensa - * hardware configuration, which is ensured by its placement in a special - * section known to the Xtensa linker support package (LSP). It performs the - * minimum necessary before jumping to the handler in the .text section. - */ - -/* Currently only shells for high priority interrupt handlers are provided - * here. However a template and example can be found in the Cadence Design - * Systems tools documentation: "Microprocessor Programmer's Guide". - */ - -#if GEN_HIGH_INTERRUPT(2) - - .begin literal_prefix .Level2InterruptVector - .section .Level2InterruptVector.text, "ax" - .global _Level2Vector - .type _Level2Vector,@function - .align 4 -_Level2Vector: - wsr a0, EXCSAVE_2 /* preserve a0 */ - call0 _xt_highint2 /* load interrupt handler */ - - .end literal_prefix - - .text - .type _xt_highint2,@function - .align 4 -_xt_highint2: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 2<<2 - beqz a0, 1f -.Ln_xt_highint2_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. */ - - .align 4 -.L_xt_highint2_exit: - rsr a0, EXCSAVE_2 /* restore a0 */ - rfi 2 - -#endif /* Level 2 */ - -#if GEN_HIGH_INTERRUPT(3) - - .begin literal_prefix .Level3InterruptVector - .section .Level3InterruptVector.text, "ax" - .global _Level3Vector - .type _Level3Vector,@function - .align 4 -_Level3Vector: - wsr a0, EXCSAVE_3 /* preserve a0 */ - call0 _xt_highint3 /* load interrupt handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .type _xt_highint3,@function - .align 4 -_xt_highint3: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 3<<2 - beqz a0, 1f -.Ln_xt_highint3_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. */ - - .align 4 -.L_xt_highint3_exit: - rsr a0, EXCSAVE_3 /* restore a0 */ - rfi 3 - -#endif /* Level 3 */ - -#if GEN_HIGH_INTERRUPT(4) - - .begin literal_prefix .Level4InterruptVector - .section .Level4InterruptVector.text, "ax" - .global _Level4Vector - .type _Level4Vector,@function - .align 4 -_Level4Vector: - wsr a0, EXCSAVE_4 /* preserve a0 */ - call0 _xt_highint4 /* load interrupt handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .type _xt_highint4,@function - .align 4 -_xt_highint4: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 4<<2 - beqz a0, 1f -.Ln_xt_highint4_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. */ - - .align 4 -.L_xt_highint4_exit: - rsr a0, EXCSAVE_4 /* restore a0 */ - rfi 4 - -#endif /* Level 4 */ - -#if GEN_HIGH_INTERRUPT(5) - .begin literal_prefix .Level5InterruptVector - .section .Level5InterruptVector.text, "ax" - .global _Level5Vector - .type _Level5Vector,@function - .align 4 -_Level5Vector: - wsr a0, EXCSAVE_5 /* preserve a0 */ - call0 _xt_highint5 /* load interrupt handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .type _xt_highint5,@function - .align 4 -_xt_highint5: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 5<<2 - beqz a0, 1f -.Ln_xt_highint5_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. - */ - - .align 4 -.L_xt_highint5_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 - -#endif /* Level 5 */ - -#if GEN_HIGH_INTERRUPT(6) - - .begin literal_prefix .Level6InterruptVector - .section .Level6InterruptVector.text, "ax" - .global _Level6Vector - .type _Level6Vector,@function - .align 4 -_Level6Vector: - wsr a0, EXCSAVE_6 /* preserve a0 */ - call0 _xt_highint6 /* load interrupt handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .type _xt_highint6,@function - .align 4 -_xt_highint6: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 6<<2 - beqz a0, 1f -.Ln_xt_highint6_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. - */ - - .align 4 -.L_xt_highint6_exit: - rsr a0, EXCSAVE_6 /* restore a0 */ - rfi 6 - -#endif /* Level 6 */ - -#if XCHAL_HAVE_NMI - - .begin literal_prefix .NMIExceptionVector - .section .NMIExceptionVector.text, "ax" - .global _NMIExceptionVector - .type _NMIExceptionVector,@function - .align 4 -_NMIExceptionVector: - wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ - call0 _xt_nmi /* load interrupt handler */ - /* never returns here - call0 is used as a jump (see note at top) */ - - .end literal_prefix - - .text - .type _xt_nmi,@function - .align 4 -_xt_nmi: - - #ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - movi a0, _xt_intexc_hooks - l32i a0, a0, XCHAL_NMILEVEL<<2 - beqz a0, 1f -.Ln_xt_nmi_call_hook: - callx0 a0 /* must NOT disturb stack! */ -1: - #endif - - /* USER_EDIT: - * ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE. - */ - - .align 4 -.L_xt_nmi_exit: - rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ - rfi XCHAL_NMILEVEL - -#endif /* NMI */ - - diff --git a/arch/xtensa/include/kernel_arch_data.h b/arch/xtensa/include/kernel_arch_data.h index f96670892fb..248494f444c 100644 --- a/arch/xtensa/include/kernel_arch_data.h +++ b/arch/xtensa/include/kernel_arch_data.h @@ -51,10 +51,8 @@ extern "C" { typedef struct __esf __esf_t; -#ifdef CONFIG_USE_SWITCH void xtensa_switch(void *switch_to, void **switched_from); #define z_arch_switch xtensa_switch -#endif #ifdef __cplusplus } diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 36ab8adecf4..713a09fc710 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -44,15 +44,11 @@ extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE); static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void) { -#ifdef CONFIG_XTENSA_ASM2 void *val; val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR); return val; -#else - return &_kernel.cpus[0]; -#endif } /** @@ -70,8 +66,6 @@ static ALWAYS_INLINE void kernel_arch_init(void) _cpu_t *cpu0 = &_kernel.cpus[0]; cpu0->nested = 0; - -#if CONFIG_XTENSA_ASM2 cpu0->irq_stack = (Z_THREAD_STACK_BUFFER(_interrupt_stack) + CONFIG_ISR_STACK_SIZE); @@ -82,14 +76,6 @@ static ALWAYS_INLINE void kernel_arch_init(void) * already is a big win. */ WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0); -#endif - -#if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0 - /* Initialize co-processor management for threads. - * Leave CPENABLE alone. - */ - z_xt_coproc_init(); -#endif #ifdef CONFIG_INIT_STACKS memset(Z_THREAD_STACK_BUFFER(_interrupt_stack), 0xAA, @@ -97,27 +83,6 @@ static ALWAYS_INLINE void kernel_arch_init(void) #endif } -/** - * - * @brief Set the return value for the specified thread (inline) - * - * @param thread pointer to thread - * @param value value to set as return value - * - * The register used to store the return value from a function call invocation - * is set to . It is assumed that the specified thread is pending, and - * thus the thread's context is stored in its k_thread. - * - * @return N/A - */ -#if !CONFIG_USE_SWITCH -static ALWAYS_INLINE void -z_set_thread_return_value(struct k_thread *thread, unsigned int value) -{ - thread->callee_saved.retval = value; -} -#endif - extern void k_cpu_atomic_idle(unsigned int key); #ifdef __cplusplus diff --git a/arch/xtensa/include/xtensa_api.h b/arch/xtensa/include/xtensa_api.h index 36e2003c08c..9d1483a105e 100644 --- a/arch/xtensa/include/xtensa_api.h +++ b/arch/xtensa/include/xtensa_api.h @@ -15,7 +15,6 @@ * * mask - Bit mask of interrupts to be enabled. */ -#if CONFIG_XTENSA_ASM2 static inline void z_xt_ints_on(unsigned int mask) { int val; @@ -24,9 +23,6 @@ static inline void z_xt_ints_on(unsigned int mask) val |= mask; __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); } -#else -extern void z_xt_ints_on(unsigned int mask); -#endif /* @@ -34,7 +30,6 @@ extern void z_xt_ints_on(unsigned int mask); * * mask - Bit mask of interrupts to be disabled. */ -#if CONFIG_XTENSA_ASM2 static inline void z_xt_ints_off(unsigned int mask) { int val; @@ -43,9 +38,6 @@ static inline void z_xt_ints_off(unsigned int mask) val &= ~mask; __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); } -#else -extern void z_xt_ints_off(unsigned int mask); -#endif /* * Call this function to set the specified (s/w) interrupt. diff --git a/boards/xtensa/xt-sim/doc/index.rst b/boards/xtensa/xt-sim/doc/index.rst index fd29ed15034..16ef7f15e50 100644 --- a/boards/xtensa/xt-sim/doc/index.rst +++ b/boards/xtensa/xt-sim/doc/index.rst @@ -25,16 +25,8 @@ Hardware The following Xtensa cores are officially supported: -- hifi3_bd5 -- XRC_FUSION_AON_ALL_LM -- D_108mini -- D_212GP -- D_233L -- hifi_mini_4swIrq (call0 ABI, added 4 SW IRQ for tests and 1 timer level 1) -- hifi2_std -- XRC_D2PM_5swIrq (added 4 SW IRQ for tests and 1 timer level 1) -- hifi4_bd7 (Big Endian) -- hifi3_bd5_call0 (call0 ABI, added 3 SW IRQs for tests) +- Intel S1000 +- sample_controller System Clock ============ diff --git a/boards/xtensa/xt-sim/xt-sim_D_108mini.yaml b/boards/xtensa/xt-sim/xt-sim_D_108mini.yaml deleted file mode 100644 index 82a1ef9e57e..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_108mini.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_D_108mini -name: XT Simulator D_108mini -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_D_108mini_defconfig b/boards/xtensa/xt-sim/xt-sim_D_108mini_defconfig deleted file mode 100644 index 228466e5e77..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_108mini_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_D_108mini=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/boards/xtensa/xt-sim/xt-sim_D_212GP.yaml b/boards/xtensa/xt-sim/xt-sim_D_212GP.yaml deleted file mode 100644 index 3eca8d0659e..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_212GP.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_D_212GP -name: XT Simulator D_212GP -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_D_212GP_defconfig b/boards/xtensa/xt-sim/xt-sim_D_212GP_defconfig deleted file mode 100644 index 1f752fef569..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_212GP_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_D_212GP=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/boards/xtensa/xt-sim/xt-sim_D_233L.yaml b/boards/xtensa/xt-sim/xt-sim_D_233L.yaml deleted file mode 100644 index 6ac91a9755f..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_233L.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_D_233L -name: XT Simulator D_233L -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_D_233L_defconfig b/boards/xtensa/xt-sim/xt-sim_D_233L_defconfig deleted file mode 100644 index 18c33f5f5f6..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_D_233L_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_D_233L=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM.yaml b/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM.yaml deleted file mode 100644 index aca99d3586f..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_XRC_FUSION_AON_ALL_LM -name: XT Simulator XRC_FUSION_AON_ALL_LM -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM_defconfig b/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM_defconfig deleted file mode 100644 index 066872ca837..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_XRC_FUSION_AON_ALL_LM_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_XRC_FUSION_AON_ALL_LM=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/boards/xtensa/xt-sim/xt-sim_hifi2_std.yaml b/boards/xtensa/xt-sim/xt-sim_hifi2_std.yaml deleted file mode 100644 index a21ae522f71..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_hifi2_std.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_hifi2_std -name: XT Simulatora hifi2_std -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_hifi2_std_defconfig b/boards/xtensa/xt-sim/xt-sim_hifi2_std_defconfig deleted file mode 100644 index 3d4904e6a59..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_hifi2_std_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_HIFI2_STD=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/boards/xtensa/xt-sim/xt-sim_hifi3_bd5.yaml b/boards/xtensa/xt-sim/xt-sim_hifi3_bd5.yaml deleted file mode 100644 index 811de30198a..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_hifi3_bd5.yaml +++ /dev/null @@ -1,6 +0,0 @@ -identifier: xt-sim_hifi3_bd5 -name: XT Simulator hifi3_bd5 -type: sim -arch: xtensa -toolchain: - - xcc diff --git a/boards/xtensa/xt-sim/xt-sim_hifi3_bd5_defconfig b/boards/xtensa/xt-sim/xt-sim_hifi3_bd5_defconfig deleted file mode 100644 index 15fa8eb2d31..00000000000 --- a/boards/xtensa/xt-sim/xt-sim_hifi3_bd5_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_IPM_CONSOLE_STACK_SIZE=2048 -CONFIG_XTENSA=y -CONFIG_SOC_HIFI3_BD5=y -CONFIG_BOARD_XT_SIM=y -CONFIG_CONSOLE=y - -CONFIG_SW_ISR_TABLE=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y diff --git a/drivers/timer/xtensa_sys_timer.c b/drivers/timer/xtensa_sys_timer.c index 16d9d1ee1ac..b0fe417faf9 100644 --- a/drivers/timer/xtensa_sys_timer.c +++ b/drivers/timer/xtensa_sys_timer.c @@ -57,17 +57,6 @@ static void ccompare_isr(void *arg) z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1); } -/* The legacy Xtensa platform code handles the timer interrupt via a - * special path and must find it via this name. Remove once ASM2 is - * pervasive. - */ -#ifndef CONFIG_XTENSA_ASM2 -void timer_int_handler(void *arg) -{ - return ccompare_isr(arg); -} -#endif - int z_clock_driver_init(struct device *device) { IRQ_CONNECT(TIMER_IRQ, 0, ccompare_isr, 0, 0); diff --git a/include/arch/xtensa/arch.h b/include/arch/xtensa/arch.h index 68739c3a98d..d6294c0cb32 100644 --- a/include/arch/xtensa/arch.h +++ b/include/arch/xtensa/arch.h @@ -78,11 +78,7 @@ extern void z_irq_priority_set(u32_t irq, u32_t prio, u32_t flags); /* Spurious interrupt handler. Throws an error if called */ extern void z_irq_spurious(void *unused); -#ifdef CONFIG_XTENSA_ASM2 -#define XTENSA_ERR_NORET /**/ -#else -#define XTENSA_ERR_NORET FUNC_NORETURN -#endif +#define XTENSA_ERR_NORET extern u32_t z_timer_cycle_get_32(void); #define z_arch_k_cycle_get_32() z_timer_cycle_get_32() diff --git a/soc/xtensa/D_108mini/Kconfig.defconfig b/soc/xtensa/D_108mini/Kconfig.defconfig deleted file mode 100644 index f44985e8d8b..00000000000 --- a/soc/xtensa/D_108mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_D_108MINI - -config SOC - string - default "D_108mini" - -config IRQ_OFFLOAD_INTNUM - default 7 - -endif diff --git a/soc/xtensa/D_108mini/Kconfig.soc b/soc/xtensa/D_108mini/Kconfig.soc deleted file mode 100644 index cdb2fef0e0f..00000000000 --- a/soc/xtensa/D_108mini/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_D_108MINI - bool "D_108mini core" diff --git a/soc/xtensa/D_108mini/linker.ld b/soc/xtensa/D_108mini/linker.ld deleted file mode 100644 index f84e77dd660..00000000000 --- a/soc/xtensa/D_108mini/linker.ld +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram0_seg :sram0_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - dram1_0_seg : org = 0x3FFC0000, len = 0x20000 - dram0_0_seg : org = 0x3FFE0000, len = 0x20000 - iram0_0_seg : org = 0x40000000, len = 0x178 - iram0_1_seg : org = 0x40000178, len = 0x8 - iram0_2_seg : org = 0x40000180, len = 0x38 - iram0_3_seg : org = 0x400001B8, len = 0x8 - iram0_4_seg : org = 0x400001C0, len = 0x38 - iram0_5_seg : org = 0x400001F8, len = 0x8 - iram0_6_seg : org = 0x40000200, len = 0x38 - iram0_7_seg : org = 0x40000238, len = 0x8 - iram0_8_seg : org = 0x40000240, len = 0x38 - iram0_9_seg : org = 0x40000278, len = 0x8 - iram0_10_seg : org = 0x40000280, len = 0x38 - iram0_11_seg : org = 0x400002B8, len = 0x8 - iram0_12_seg : org = 0x400002C0, len = 0x38 - iram0_13_seg : org = 0x400002F8, len = 0x8 - iram0_14_seg : org = 0x40000300, len = 0x38 - iram0_15_seg : org = 0x40000338, len = 0x8 - iram0_16_seg : org = 0x40000340, len = 0x38 - iram0_17_seg : org = 0x40000378, len = 0x48 - iram0_18_seg : org = 0x400003C0, len = 0x40 - iram0_19_seg : org = 0x40000400, len = 0x1FC00 - srom0_seg : org = 0x50000000, len = 0x300 - srom1_seg : org = 0x50000300, len = 0xFFFD00 - sram0_seg : org = 0x60000000, len = 0x4000000 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3ffbe000, len = 0x2000 -#endif -} - -PHDRS -{ - dram1_0_phdr PT_LOAD; - dram1_0_bss_phdr PT_LOAD; - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - iram0_1_phdr PT_LOAD; - iram0_2_phdr PT_LOAD; - iram0_3_phdr PT_LOAD; - iram0_4_phdr PT_LOAD; - iram0_5_phdr PT_LOAD; - iram0_6_phdr PT_LOAD; - iram0_7_phdr PT_LOAD; - iram0_8_phdr PT_LOAD; - iram0_9_phdr PT_LOAD; - iram0_10_phdr PT_LOAD; - iram0_11_phdr PT_LOAD; - iram0_12_phdr PT_LOAD; - iram0_13_phdr PT_LOAD; - iram0_14_phdr PT_LOAD; - iram0_15_phdr PT_LOAD; - iram0_16_phdr PT_LOAD; - iram0_17_phdr PT_LOAD; - iram0_18_phdr PT_LOAD; - iram0_19_phdr PT_LOAD; - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram0_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dram1_start = 0x3ffc0000; -_memmap_mem_dram1_end = 0x3ffe0000; -_memmap_mem_dram0_start = 0x3ffe0000; -_memmap_mem_dram0_end = 0x40000000; -_memmap_mem_iram0_start = 0x40000000; -_memmap_mem_iram0_end = 0x40020000; -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dram1_0_start = 0x3ffc0000; -_memmap_seg_dram1_0_max = 0x3ffe0000; -_memmap_seg_dram0_0_start = 0x3ffe0000; -_memmap_seg_dram0_0_max = 0x40000000; -_memmap_seg_iram0_0_start = 0x40000000; -_memmap_seg_iram0_0_max = 0x40000178; -_memmap_seg_iram0_1_start = 0x40000178; -_memmap_seg_iram0_1_max = 0x40000180; -_memmap_seg_iram0_2_start = 0x40000180; -_memmap_seg_iram0_2_max = 0x400001b8; -_memmap_seg_iram0_3_start = 0x400001b8; -_memmap_seg_iram0_3_max = 0x400001c0; -_memmap_seg_iram0_4_start = 0x400001c0; -_memmap_seg_iram0_4_max = 0x400001f8; -_memmap_seg_iram0_5_start = 0x400001f8; -_memmap_seg_iram0_5_max = 0x40000200; -_memmap_seg_iram0_6_start = 0x40000200; -_memmap_seg_iram0_6_max = 0x40000238; -_memmap_seg_iram0_7_start = 0x40000238; -_memmap_seg_iram0_7_max = 0x40000240; -_memmap_seg_iram0_8_start = 0x40000240; -_memmap_seg_iram0_8_max = 0x40000278; -_memmap_seg_iram0_9_start = 0x40000278; -_memmap_seg_iram0_9_max = 0x40000280; -_memmap_seg_iram0_10_start = 0x40000280; -_memmap_seg_iram0_10_max = 0x400002b8; -_memmap_seg_iram0_11_start = 0x400002b8; -_memmap_seg_iram0_11_max = 0x400002c0; -_memmap_seg_iram0_12_start = 0x400002c0; -_memmap_seg_iram0_12_max = 0x400002f8; -_memmap_seg_iram0_13_start = 0x400002f8; -_memmap_seg_iram0_13_max = 0x40000300; -_memmap_seg_iram0_14_start = 0x40000300; -_memmap_seg_iram0_14_max = 0x40000338; -_memmap_seg_iram0_15_start = 0x40000338; -_memmap_seg_iram0_15_max = 0x40000340; -_memmap_seg_iram0_16_start = 0x40000340; -_memmap_seg_iram0_16_max = 0x40000378; -_memmap_seg_iram0_17_start = 0x40000378; -_memmap_seg_iram0_17_max = 0x400003c0; -_memmap_seg_iram0_18_start = 0x400003c0; -_memmap_seg_iram0_18_max = 0x40000400; -_memmap_seg_iram0_19_start = 0x40000400; -_memmap_seg_iram0_19_max = 0x40020000; -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x50000300; -_memmap_seg_srom1_start = 0x50000300; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x40000000); -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00001110; -_memmap_cacheattr_wt_base = 0x00001110; -_memmap_cacheattr_bp_base = 0x00002220; -_memmap_cacheattr_unused_mask = 0xFFFF000F; -_memmap_cacheattr_wb_trapnull = 0x2222111F; -_memmap_cacheattr_wba_trapnull = 0x2222111F; -_memmap_cacheattr_wbna_trapnull = 0x2222111F; -_memmap_cacheattr_wt_trapnull = 0x2222111F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF111F; -_memmap_cacheattr_wt_strict = 0xFFFF111F; -_memmap_cacheattr_bp_strict = 0xFFFF222F; -_memmap_cacheattr_wb_allvalid = 0x22221112; -_memmap_cacheattr_wt_allvalid = 0x22221112; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .dram1.rodata : ALIGN(4) - { - _dram1_rodata_start = ABSOLUTE(.); - *(.dram1.rodata) - _dram1_rodata_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.literal : ALIGN(4) - { - _dram1_literal_start = ABSOLUTE(.); - *(.dram1.literal) - _dram1_literal_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.data : ALIGN(4) - { - _dram1_data_start = ABSOLUTE(.); - *(.dram1.data) - _dram1_data_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram1_bss_start = ABSOLUTE(.); - *(.dram1.bss) - . = ALIGN (8); - _dram1_bss_end = ABSOLUTE(.); - _memmap_seg_dram1_0_end = ALIGN(0x8); - } >dram1_0_seg :dram1_0_bss_phdr - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - *(.dram0.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram0_bss_start = ABSOLUTE(.); - *(.dram0.bss) - . = ALIGN (8); - _dram0_bss_end = ABSOLUTE(.); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - } >iram0_0_seg :iram0_0_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_1_end = ALIGN(0x8); - } >iram0_1_seg :iram0_1_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_2_end = ALIGN(0x8); - } >iram0_2_seg :iram0_2_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_3_end = ALIGN(0x8); - } >iram0_3_seg :iram0_3_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_4_end = ALIGN(0x8); - } >iram0_4_seg :iram0_4_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_5_end = ALIGN(0x8); - } >iram0_5_seg :iram0_5_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_6_end = ALIGN(0x8); - } >iram0_6_seg :iram0_6_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_7_end = ALIGN(0x8); - } >iram0_7_seg :iram0_7_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_8_end = ALIGN(0x8); - } >iram0_8_seg :iram0_8_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_9_end = ALIGN(0x8); - } >iram0_9_seg :iram0_9_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_10_end = ALIGN(0x8); - } >iram0_10_seg :iram0_10_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_11_end = ALIGN(0x8); - } >iram0_11_seg :iram0_11_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_12_end = ALIGN(0x8); - } >iram0_12_seg :iram0_12_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_13_end = ALIGN(0x8); - } >iram0_13_seg :iram0_13_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_14_end = ALIGN(0x8); - } >iram0_14_seg :iram0_14_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_15_end = ALIGN(0x8); - } >iram0_15_seg :iram0_15_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_16_end = ALIGN(0x8); - } >iram0_16_seg :iram0_16_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_17_end = ALIGN(0x8); - } >iram0_17_seg :iram0_17_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_18_end = ALIGN(0x8); - } >iram0_18_seg :iram0_18_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - _iram0_text_end = ABSOLUTE(.); - _memmap_seg_iram0_19_end = ALIGN(0x8); - } >iram0_19_seg :iram0_19_phdr - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_dram1_bss_start) - LONG(_dram1_bss_end) - LONG(_dram0_bss_start) - LONG(_dram0_bss_end) - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram0_seg :sram0_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram0_seg :sram0_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_bss_phdr - __stack = 0x64000000; - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/D_212GP/Kconfig.defconfig b/soc/xtensa/D_212GP/Kconfig.defconfig deleted file mode 100644 index 77bc6ccc2e7..00000000000 --- a/soc/xtensa/D_212GP/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_D_212GP - -config SOC - string - default "D_212GP" - -config IRQ_OFFLOAD_INTNUM - default 7 - -endif diff --git a/soc/xtensa/D_212GP/Kconfig.soc b/soc/xtensa/D_212GP/Kconfig.soc deleted file mode 100644 index 5cbe8b36826..00000000000 --- a/soc/xtensa/D_212GP/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_D_212GP - bool "D_212GP core" diff --git a/soc/xtensa/D_212GP/linker.ld b/soc/xtensa/D_212GP/linker.ld deleted file mode 100644 index 412e87bd651..00000000000 --- a/soc/xtensa/D_212GP/linker.ld +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram19_seg :sram19_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - dport0_0_seg : org = 0x3FFC0000, len = 0x20000 - dram0_0_seg : org = 0x3FFE0000, len = 0x20000 - iram0_0_seg : org = 0x40000000, len = 0x20000 - srom0_seg : org = 0x50000000, len = 0x300 - srom1_seg : org = 0x50000300, len = 0xFFFD00 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x8 - sram2_seg : org = 0x60000180, len = 0x38 - sram3_seg : org = 0x600001B8, len = 0x8 - sram4_seg : org = 0x600001C0, len = 0x38 - sram5_seg : org = 0x600001F8, len = 0x8 - sram6_seg : org = 0x60000200, len = 0x38 - sram7_seg : org = 0x60000238, len = 0x8 - sram8_seg : org = 0x60000240, len = 0x38 - sram9_seg : org = 0x60000278, len = 0x8 - sram10_seg : org = 0x60000280, len = 0x38 - sram11_seg : org = 0x600002B8, len = 0x8 - sram12_seg : org = 0x600002C0, len = 0x38 - sram13_seg : org = 0x600002F8, len = 0x8 - sram14_seg : org = 0x60000300, len = 0x38 - sram15_seg : org = 0x60000338, len = 0x8 - sram16_seg : org = 0x60000340, len = 0x38 - sram17_seg : org = 0x60000378, len = 0x48 - sram18_seg : org = 0x600003C0, len = 0x40 - sram19_seg : org = 0x60000400, len = 0x3FFFC00 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3ffbe000, len = 0x2000 -#endif -} - -PHDRS -{ - dport0_0_phdr PT_LOAD; - dport0_0_bss_phdr PT_LOAD; - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram10_phdr PT_LOAD; - sram11_phdr PT_LOAD; - sram12_phdr PT_LOAD; - sram13_phdr PT_LOAD; - sram14_phdr PT_LOAD; - sram15_phdr PT_LOAD; - sram16_phdr PT_LOAD; - sram17_phdr PT_LOAD; - sram18_phdr PT_LOAD; - sram19_phdr PT_LOAD; - sram19_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dport0_start = 0x3ffc0000; -_memmap_mem_dport0_end = 0x3ffe0000; -_memmap_mem_dram0_start = 0x3ffe0000; -_memmap_mem_dram0_end = 0x40000000; -_memmap_mem_iram0_start = 0x40000000; -_memmap_mem_iram0_end = 0x40020000; -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dport0_0_start = 0x3ffc0000; -_memmap_seg_dport0_0_max = 0x3ffe0000; -_memmap_seg_dram0_0_start = 0x3ffe0000; -_memmap_seg_dram0_0_max = 0x40000000; -_memmap_seg_iram0_0_start = 0x40000000; -_memmap_seg_iram0_0_max = 0x40020000; -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x50000300; -_memmap_seg_srom1_start = 0x50000300; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x60000180; -_memmap_seg_sram2_start = 0x60000180; -_memmap_seg_sram2_max = 0x600001b8; -_memmap_seg_sram3_start = 0x600001b8; -_memmap_seg_sram3_max = 0x600001c0; -_memmap_seg_sram4_start = 0x600001c0; -_memmap_seg_sram4_max = 0x600001f8; -_memmap_seg_sram5_start = 0x600001f8; -_memmap_seg_sram5_max = 0x60000200; -_memmap_seg_sram6_start = 0x60000200; -_memmap_seg_sram6_max = 0x60000238; -_memmap_seg_sram7_start = 0x60000238; -_memmap_seg_sram7_max = 0x60000240; -_memmap_seg_sram8_start = 0x60000240; -_memmap_seg_sram8_max = 0x60000278; -_memmap_seg_sram9_start = 0x60000278; -_memmap_seg_sram9_max = 0x60000280; -_memmap_seg_sram10_start = 0x60000280; -_memmap_seg_sram10_max = 0x600002b8; -_memmap_seg_sram11_start = 0x600002b8; -_memmap_seg_sram11_max = 0x600002c0; -_memmap_seg_sram12_start = 0x600002c0; -_memmap_seg_sram12_max = 0x600002f8; -_memmap_seg_sram13_start = 0x600002f8; -_memmap_seg_sram13_max = 0x60000300; -_memmap_seg_sram14_start = 0x60000300; -_memmap_seg_sram14_max = 0x60000338; -_memmap_seg_sram15_start = 0x60000338; -_memmap_seg_sram15_max = 0x60000340; -_memmap_seg_sram16_start = 0x60000340; -_memmap_seg_sram16_max = 0x60000378; -_memmap_seg_sram17_start = 0x60000378; -_memmap_seg_sram17_max = 0x600003c0; -_memmap_seg_sram18_start = 0x600003c0; -_memmap_seg_sram18_max = 0x60000400; -_memmap_seg_sram19_start = 0x60000400; -_memmap_seg_sram19_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x60000000); -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00004440; -_memmap_cacheattr_wt_base = 0x00001110; -_memmap_cacheattr_bp_base = 0x00002220; -_memmap_cacheattr_unused_mask = 0xFFFF000F; -_memmap_cacheattr_wb_trapnull = 0x2222444F; -_memmap_cacheattr_wba_trapnull = 0x2222444F; -_memmap_cacheattr_wbna_trapnull = 0x2222555F; -_memmap_cacheattr_wt_trapnull = 0x2222111F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF444F; -_memmap_cacheattr_wt_strict = 0xFFFF111F; -_memmap_cacheattr_bp_strict = 0xFFFF222F; -_memmap_cacheattr_wb_allvalid = 0x22224442; -_memmap_cacheattr_wt_allvalid = 0x22221112; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .dport0.rodata : ALIGN(4) - { - _dport0_rodata_start = ABSOLUTE(.); - *(.dport0.rodata) - *(.dport.rodata) - _dport0_rodata_end = ABSOLUTE(.); - } >dport0_0_seg :dport0_0_phdr - - .dport0.literal : ALIGN(4) - { - _dport0_literal_start = ABSOLUTE(.); - *(.dport0.literal) - *(.dport.literal) - _dport0_literal_end = ABSOLUTE(.); - } >dport0_0_seg :dport0_0_phdr - - .dport0.data : ALIGN(4) - { - _dport0_data_start = ABSOLUTE(.); - *(.dport0.data) - *(.dport.data) - _dport0_data_end = ABSOLUTE(.); - } >dport0_0_seg :dport0_0_phdr - - .dport0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dport0_bss_start = ABSOLUTE(.); - *(.dport0.bss) - . = ALIGN (8); - _dport0_bss_end = ABSOLUTE(.); - _memmap_seg_dport0_0_end = ALIGN(0x8); - } >dport0_0_seg :dport0_0_bss_phdr - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - *(.dram0.rodata) - *(.dram.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - *(.dram.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - *(.dram.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram0_bss_start = ABSOLUTE(.); - *(.dram0.bss) - . = ALIGN (8); - _dram0_bss_end = ABSOLUTE(.); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - _iram0_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - } >iram0_0_seg :iram0_0_phdr - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram10_end = ALIGN(0x8); - } >sram10_seg :sram10_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram11_end = ALIGN(0x8); - } >sram11_seg :sram11_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram12_end = ALIGN(0x8); - } >sram12_seg :sram12_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram13_end = ALIGN(0x8); - } >sram13_seg :sram13_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram14_end = ALIGN(0x8); - } >sram14_seg :sram14_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram15_end = ALIGN(0x8); - } >sram15_seg :sram15_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram16_end = ALIGN(0x8); - } >sram16_seg :sram16_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram17_end = ALIGN(0x8); - } >sram17_seg :sram17_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram18_end = ALIGN(0x8); - } >sram18_seg :sram18_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_dport0_bss_start) - LONG(_dport0_bss_end) - LONG(_dram0_bss_start) - LONG(_dram0_bss_end) - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram19_seg :sram19_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram19_seg :sram19_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram19_end = ALIGN(0x8); - } >sram19_seg :sram19_bss_phdr - __stack = 0x64000000; - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/D_233L/Kconfig.defconfig b/soc/xtensa/D_233L/Kconfig.defconfig deleted file mode 100644 index da31e34abce..00000000000 --- a/soc/xtensa/D_233L/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_D_233L - -config SOC - string - default "D_233L" - -config IRQ_OFFLOAD_INTNUM - default 7 - -endif diff --git a/soc/xtensa/D_233L/Kconfig.soc b/soc/xtensa/D_233L/Kconfig.soc deleted file mode 100644 index 36e6143ec06..00000000000 --- a/soc/xtensa/D_233L/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_D_233L - bool "D_233L core" diff --git a/soc/xtensa/D_233L/linker.ld b/soc/xtensa/D_233L/linker.ld deleted file mode 100644 index 2f826603014..00000000000 --- a/soc/xtensa/D_233L/linker.ld +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram20_seg :sram20_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - sram1_seg : org = 0x00002000, len = 0x178 - sram2_seg : org = 0x00002178, len = 0x8 - sram3_seg : org = 0x00002180, len = 0x38 - sram4_seg : org = 0x000021B8, len = 0x8 - sram5_seg : org = 0x000021C0, len = 0x38 - sram6_seg : org = 0x000021F8, len = 0x8 - sram7_seg : org = 0x00002200, len = 0x38 - sram8_seg : org = 0x00002238, len = 0x8 - sram9_seg : org = 0x00002240, len = 0x38 - sram10_seg : org = 0x00002278, len = 0x8 - sram11_seg : org = 0x00002280, len = 0x38 - sram12_seg : org = 0x000022B8, len = 0x8 - sram13_seg : org = 0x000022C0, len = 0x38 - sram14_seg : org = 0x000022F8, len = 0x8 - sram15_seg : org = 0x00002300, len = 0x38 - sram16_seg : org = 0x00002338, len = 0x8 - sram17_seg : org = 0x00002340, len = 0x38 - sram18_seg : org = 0x00002378, len = 0x48 - sram19_seg : org = 0x000023C0, len = 0x140 - sram20_seg : org = 0x00002500, len = 0x3FFDB00 - srom0_seg : org = 0xFE000000, len = 0x300 - srom1_seg : org = 0xFE000300, len = 0xFFFD00 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3ffdd50, len = 0x2000 -#endif -} - -PHDRS -{ - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram10_phdr PT_LOAD; - sram11_phdr PT_LOAD; - sram12_phdr PT_LOAD; - sram13_phdr PT_LOAD; - sram14_phdr PT_LOAD; - sram15_phdr PT_LOAD; - sram16_phdr PT_LOAD; - sram17_phdr PT_LOAD; - sram18_phdr PT_LOAD; - sram19_phdr PT_LOAD; - sram20_phdr PT_LOAD; - sram20_bss_phdr PT_LOAD; - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_sram_start = 0x4; -_memmap_mem_sram_end = 0x4000000; -_memmap_mem_srom_start = 0xfe000000; -_memmap_mem_srom_end = 0xff000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_sram1_start = 0x2000; -_memmap_seg_sram1_max = 0x2178; -_memmap_seg_sram2_start = 0x2178; -_memmap_seg_sram2_max = 0x2180; -_memmap_seg_sram3_start = 0x2180; -_memmap_seg_sram3_max = 0x21b8; -_memmap_seg_sram4_start = 0x21b8; -_memmap_seg_sram4_max = 0x21c0; -_memmap_seg_sram5_start = 0x21c0; -_memmap_seg_sram5_max = 0x21f8; -_memmap_seg_sram6_start = 0x21f8; -_memmap_seg_sram6_max = 0x2200; -_memmap_seg_sram7_start = 0x2200; -_memmap_seg_sram7_max = 0x2238; -_memmap_seg_sram8_start = 0x2238; -_memmap_seg_sram8_max = 0x2240; -_memmap_seg_sram9_start = 0x2240; -_memmap_seg_sram9_max = 0x2278; -_memmap_seg_sram10_start = 0x2278; -_memmap_seg_sram10_max = 0x2280; -_memmap_seg_sram11_start = 0x2280; -_memmap_seg_sram11_max = 0x22b8; -_memmap_seg_sram12_start = 0x22b8; -_memmap_seg_sram12_max = 0x22c0; -_memmap_seg_sram13_start = 0x22c0; -_memmap_seg_sram13_max = 0x22f8; -_memmap_seg_sram14_start = 0x22f8; -_memmap_seg_sram14_max = 0x2300; -_memmap_seg_sram15_start = 0x2300; -_memmap_seg_sram15_max = 0x2338; -_memmap_seg_sram16_start = 0x2338; -_memmap_seg_sram16_max = 0x2340; -_memmap_seg_sram17_start = 0x2340; -_memmap_seg_sram17_max = 0x2378; -_memmap_seg_sram18_start = 0x2378; -_memmap_seg_sram18_max = 0x23c0; -_memmap_seg_sram19_start = 0x23c0; -_memmap_seg_sram19_max = 0x2500; -_memmap_seg_sram20_start = 0x2500; -_memmap_seg_sram20_max = 0x4000000; -_memmap_seg_srom0_start = 0xfe000000; -_memmap_seg_srom0_max = 0xfe000300; -_memmap_seg_srom1_start = 0xfe000300; -_memmap_seg_srom1_max = 0xff000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x2000); -PROVIDE(_memmap_reset_vector = 0xfe000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x70000007; -_memmap_cacheattr_wt_base = 0xB000000B; -_memmap_cacheattr_bp_base = 0x30000003; -_memmap_cacheattr_unused_mask = 0x0FFFFFF0; -_memmap_cacheattr_wb_trapnull = 0x73333337; -_memmap_cacheattr_wba_trapnull = 0x73333337; -_memmap_cacheattr_wbna_trapnull = 0x73333337; -_memmap_cacheattr_wt_trapnull = 0xB333333B; -_memmap_cacheattr_bp_trapnull = 0x33333333; -_memmap_cacheattr_wb_strict = 0x7CCCCCC7; -_memmap_cacheattr_wt_strict = 0xBCCCCCCB; -_memmap_cacheattr_bp_strict = 0x3CCCCCC3; -_memmap_cacheattr_wb_allvalid = 0x73333337; -_memmap_cacheattr_wt_allvalid = 0xB333333B; -_memmap_cacheattr_bp_allvalid = 0x33333333; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram10_end = ALIGN(0x8); - } >sram10_seg :sram10_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram11_end = ALIGN(0x8); - } >sram11_seg :sram11_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram12_end = ALIGN(0x8); - } >sram12_seg :sram12_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram13_end = ALIGN(0x8); - } >sram13_seg :sram13_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram14_end = ALIGN(0x8); - } >sram14_seg :sram14_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram15_end = ALIGN(0x8); - } >sram15_seg :sram15_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram16_end = ALIGN(0x8); - } >sram16_seg :sram16_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram17_end = ALIGN(0x8); - } >sram17_seg :sram17_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram18_end = ALIGN(0x8); - } >sram18_seg :sram18_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram19_end = ALIGN(0x8); - } >sram19_seg :sram19_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram20_seg :sram20_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram20_seg :sram20_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram20_seg :sram20_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram20_seg :sram20_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram20_seg :sram20_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram20_seg :sram20_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram20_seg :sram20_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram20_end = ALIGN(0x8); - } >sram20_seg :sram20_bss_phdr - __stack = 0x4000000; - _heap_sentry = 0x4000000; - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } - -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.defconfig b/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.defconfig deleted file mode 100644 index 1a534bd4b4f..00000000000 --- a/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XRC_D2PM_5SWIRQ - -config SOC - string - default "XRC_D2PM_5swIrq" - -config IRQ_OFFLOAD_INTNUM - default 22 - -endif diff --git a/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.soc b/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.soc deleted file mode 100644 index 0e382655221..00000000000 --- a/soc/xtensa/XRC_D2PM_5swIrq/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XRC_D2PM_5SWIRQ - bool "XRC_D2PM_5swIrq (XRC_D2PM core with 4 additional SW IRQs)" diff --git a/soc/xtensa/XRC_D2PM_5swIrq/linker.ld b/soc/xtensa/XRC_D2PM_5swIrq/linker.ld deleted file mode 100644 index e3d50e85337..00000000000 --- a/soc/xtensa/XRC_D2PM_5swIrq/linker.ld +++ /dev/null @@ -1,621 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram19_seg :sram19_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - srom0_seg : org = 0x40000000, len = 0x2E0 - srom1_seg : org = 0x400002E0, len = 0xFFFD20 - dram0_0_seg : org = 0x5FFA0000, len = 0x20000 - dram1_0_seg : org = 0x5FFC0000, len = 0x20000 - iram0_0_seg : org = 0x5FFE0000, len = 0x20000 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x4 - sram2_seg : org = 0x6000017C, len = 0x1C - sram3_seg : org = 0x60000198, len = 0x4 - sram4_seg : org = 0x6000019C, len = 0x1C - sram5_seg : org = 0x600001B8, len = 0x4 - sram6_seg : org = 0x600001BC, len = 0x1C - sram7_seg : org = 0x600001D8, len = 0x4 - sram8_seg : org = 0x600001DC, len = 0x1C - sram9_seg : org = 0x600001F8, len = 0x4 - sram10_seg : org = 0x600001FC, len = 0x1C - sram11_seg : org = 0x60000218, len = 0x4 - sram12_seg : org = 0x6000021C, len = 0x1C - sram13_seg : org = 0x60000238, len = 0x4 - sram14_seg : org = 0x6000023C, len = 0x1C - sram15_seg : org = 0x60000258, len = 0x4 - sram16_seg : org = 0x6000025C, len = 0x1C - sram17_seg : org = 0x60000278, len = 0x4 - sram18_seg : org = 0x6000027C, len = 0x1C - sram19_seg : org = 0x60000298, len = 0x3FFFD68 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - dram1_0_phdr PT_LOAD; - dram1_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram10_phdr PT_LOAD; - sram11_phdr PT_LOAD; - sram12_phdr PT_LOAD; - sram13_phdr PT_LOAD; - sram14_phdr PT_LOAD; - sram15_phdr PT_LOAD; - sram16_phdr PT_LOAD; - sram17_phdr PT_LOAD; - sram18_phdr PT_LOAD; - sram19_phdr PT_LOAD; - sram19_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_srom_start = 0x40000000; -_memmap_mem_srom_end = 0x41000000; -_memmap_mem_dram0_start = 0x5ffa0000; -_memmap_mem_dram0_end = 0x5ffc0000; -_memmap_mem_dram1_start = 0x5ffc0000; -_memmap_mem_dram1_end = 0x5ffe0000; -_memmap_mem_iram0_start = 0x5ffe0000; -_memmap_mem_iram0_end = 0x60000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_srom0_start = 0x40000000; -_memmap_seg_srom0_max = 0x400002e0; -_memmap_seg_srom1_start = 0x400002e0; -_memmap_seg_srom1_max = 0x41000000; -_memmap_seg_dram0_0_start = 0x5ffa0000; -_memmap_seg_dram0_0_max = 0x5ffc0000; -_memmap_seg_dram1_0_start = 0x5ffc0000; -_memmap_seg_dram1_0_max = 0x5ffe0000; -_memmap_seg_iram0_0_start = 0x5ffe0000; -_memmap_seg_iram0_0_max = 0x60000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x6000017c; -_memmap_seg_sram2_start = 0x6000017c; -_memmap_seg_sram2_max = 0x60000198; -_memmap_seg_sram3_start = 0x60000198; -_memmap_seg_sram3_max = 0x6000019c; -_memmap_seg_sram4_start = 0x6000019c; -_memmap_seg_sram4_max = 0x600001b8; -_memmap_seg_sram5_start = 0x600001b8; -_memmap_seg_sram5_max = 0x600001bc; -_memmap_seg_sram6_start = 0x600001bc; -_memmap_seg_sram6_max = 0x600001d8; -_memmap_seg_sram7_start = 0x600001d8; -_memmap_seg_sram7_max = 0x600001dc; -_memmap_seg_sram8_start = 0x600001dc; -_memmap_seg_sram8_max = 0x600001f8; -_memmap_seg_sram9_start = 0x600001f8; -_memmap_seg_sram9_max = 0x600001fc; -_memmap_seg_sram10_start = 0x600001fc; -_memmap_seg_sram10_max = 0x60000218; -_memmap_seg_sram11_start = 0x60000218; -_memmap_seg_sram11_max = 0x6000021c; -_memmap_seg_sram12_start = 0x6000021c; -_memmap_seg_sram12_max = 0x60000238; -_memmap_seg_sram13_start = 0x60000238; -_memmap_seg_sram13_max = 0x6000023c; -_memmap_seg_sram14_start = 0x6000023c; -_memmap_seg_sram14_max = 0x60000258; -_memmap_seg_sram15_start = 0x60000258; -_memmap_seg_sram15_max = 0x6000025c; -_memmap_seg_sram16_start = 0x6000025c; -_memmap_seg_sram16_max = 0x60000278; -_memmap_seg_sram17_start = 0x60000278; -_memmap_seg_sram17_max = 0x6000027c; -_memmap_seg_sram18_start = 0x6000027c; -_memmap_seg_sram18_max = 0x60000298; -_memmap_seg_sram19_start = 0x60000298; -_memmap_seg_sram19_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x60000000); -PROVIDE(_memmap_reset_vector = 0x40000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00001100; -_memmap_cacheattr_wt_base = 0x00001100; -_memmap_cacheattr_bp_base = 0x00002200; -_memmap_cacheattr_unused_mask = 0xFFFF00FF; -_memmap_cacheattr_wb_trapnull = 0x2222112F; -_memmap_cacheattr_wba_trapnull = 0x2222112F; -_memmap_cacheattr_wbna_trapnull = 0x2222112F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF11FF; -_memmap_cacheattr_wt_strict = 0xFFFF11FF; -_memmap_cacheattr_bp_strict = 0xFFFF22FF; -_memmap_cacheattr_wb_allvalid = 0x22221122; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - } >srom1_seg :srom1_phdr - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - *(.dram0.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram0_bss_start = ABSOLUTE(.); - *(.dram0.bss) - . = ALIGN (8); - _dram0_bss_end = ABSOLUTE(.); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - - .dram1.rodata : ALIGN(4) - { - _dram1_rodata_start = ABSOLUTE(.); - *(.dram1.rodata) - _dram1_rodata_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .iram0.literal : ALIGN(4) - { - _iram0_literal_start = ABSOLUTE(.); - *(.iram0.literal) - *(.iram.literal) - *(.iram.text.literal) - _iram0_literal_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.literal : ALIGN(4) - { - _dram1_literal_start = ABSOLUTE(.); - *(.dram1.literal) - _dram1_literal_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.data : ALIGN(4) - { - _dram1_data_start = ABSOLUTE(.); - *(.dram1.data) - _dram1_data_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram1_bss_start = ABSOLUTE(.); - *(.dram1.bss) - . = ALIGN (8); - _dram1_bss_end = ABSOLUTE(.); - _memmap_seg_dram1_0_end = ALIGN(0x8); - } >dram1_0_seg :dram1_0_bss_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.text) - *(.iram.text) - _iram0_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >iram0_0_seg :iram0_0_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram10_end = ALIGN(0x8); - } >sram10_seg :sram10_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram11_end = ALIGN(0x8); - } >sram11_seg :sram11_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram12_end = ALIGN(0x8); - } >sram12_seg :sram12_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram13_end = ALIGN(0x8); - } >sram13_seg :sram13_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram14_end = ALIGN(0x8); - } >sram14_seg :sram14_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram15_end = ALIGN(0x8); - } >sram15_seg :sram15_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram16_end = ALIGN(0x8); - } >sram16_seg :sram16_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram17_end = ALIGN(0x8); - } >sram17_seg :sram17_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram18_end = ALIGN(0x8); - } >sram18_seg :sram18_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_dram0_bss_start) - LONG(_dram0_bss_end) - LONG(_dram1_bss_start) - LONG(_dram1_bss_end) - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram19_seg :sram19_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram19_seg :sram19_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram19_end = ALIGN(0x8); - } >sram19_seg :sram19_bss_phdr - PROVIDE(__stack = 0x64000000); - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.defconfig b/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.defconfig deleted file mode 100644 index ad952934f75..00000000000 --- a/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XRC_FUSION_AON_ALL_LM - -config SOC - string - default "XRC_FUSION_AON_ALL_LM" - -config IRQ_OFFLOAD_INTNUM - default 13 - -endif diff --git a/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.soc b/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.soc deleted file mode 100644 index b9b1b0e077e..00000000000 --- a/soc/xtensa/XRC_FUSION_AON_ALL_LM/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XRC_FUSION_AON_ALL_LM - bool "XRC_FUSION_AON_ALL_LM core" diff --git a/soc/xtensa/XRC_FUSION_AON_ALL_LM/linker.ld b/soc/xtensa/XRC_FUSION_AON_ALL_LM/linker.ld deleted file mode 100644 index a84451ed6b8..00000000000 --- a/soc/xtensa/XRC_FUSION_AON_ALL_LM/linker.ld +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram0_seg :sram0_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - dram0_0_seg : org = 0x3FFE0000, len = 0x20000 - iram0_0_seg : org = 0x40000000, len = 0x178 - iram0_2_seg : org = 0x40000180, len = 0x38 - iram0_4_seg : org = 0x400001C0, len = 0x38 - iram0_6_seg : org = 0x40000200, len = 0x38 - iram0_8_seg : org = 0x40000280, len = 0x40 - iram0_9_seg : org = 0x400002C0, len = 0x1FD40 - srom0_seg : org = 0x50000000, len = 0x300 - srom1_seg : org = 0x50000300, len = 0xFFFD00 - sram0_seg : org = 0x60000000, len = 0x4000000 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3ffde000, len = 0x2000 -#endif -} - -PHDRS -{ - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - iram0_1_phdr PT_LOAD; - iram0_2_phdr PT_LOAD; - iram0_3_phdr PT_LOAD; - iram0_4_phdr PT_LOAD; - iram0_5_phdr PT_LOAD; - iram0_6_phdr PT_LOAD; - iram0_7_phdr PT_LOAD; - iram0_8_phdr PT_LOAD; - iram0_9_phdr PT_LOAD; - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram0_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dram0_start = 0x3ffe0000; -_memmap_mem_dram0_end = 0x40000000; -_memmap_mem_iram0_start = 0x40000000; -_memmap_mem_iram0_end = 0x40020000; -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dram0_0_start = 0x3ffe0000; -_memmap_seg_dram0_0_max = 0x40000000; -_memmap_seg_iram0_0_start = 0x40000000; -_memmap_seg_iram0_0_max = 0x40000178; -_memmap_seg_iram0_2_start = 0x40000180; -_memmap_seg_iram0_2_max = 0x400001b8; -_memmap_seg_iram0_4_start = 0x400001c0; -_memmap_seg_iram0_4_max = 0x400001f8; -_memmap_seg_iram0_6_start = 0x40000200; -_memmap_seg_iram0_6_max = 0x40000238; -_memmap_seg_iram0_8_start = 0x40000280; -_memmap_seg_iram0_8_max = 0x400002c0; -_memmap_seg_iram0_9_start = 0x400002c0; -_memmap_seg_iram0_9_max = 0x40020000; -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x50000300; -_memmap_seg_srom1_start = 0x50000300; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x40000000); -PROVIDE(_memmap_reset_vector = 0x50000000); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00001120; -_memmap_cacheattr_wt_base = 0x00001120; -_memmap_cacheattr_bp_base = 0x00002220; -_memmap_cacheattr_unused_mask = 0xFFFF000F; -_memmap_cacheattr_wb_trapnull = 0x2222112F; -_memmap_cacheattr_wba_trapnull = 0x2222112F; -_memmap_cacheattr_wbna_trapnull = 0x2222112F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF112F; -_memmap_cacheattr_wt_strict = 0xFFFF112F; -_memmap_cacheattr_bp_strict = 0xFFFF222F; -_memmap_cacheattr_wb_allvalid = 0x22221122; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - *(.dram0.rodata) - *(.dram.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .iram0.literal : ALIGN(4) - { - _iram0_literal_start = ABSOLUTE(.); - *(.iram0.literal) - *(.iram.literal) - *(.iram.text.literal) - _iram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - *(.dram.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - *(.dram.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram0_bss_start = ABSOLUTE(.); - *(.dram0.bss) - . = ALIGN (8); - _dram0_bss_end = ABSOLUTE(.); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - } >iram0_0_seg :iram0_0_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_2_end = ALIGN(0x8); - } >iram0_2_seg :iram0_2_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_4_end = ALIGN(0x8); - } >iram0_4_seg :iram0_4_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_6_end = ALIGN(0x8); - } >iram0_6_seg :iram0_6_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_8_end = ALIGN(0x8); - } >iram0_8_seg :iram0_8_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.text) - *(.iram.text) - _iram0_text_end = ABSOLUTE(.); - _memmap_seg_iram0_9_end = ALIGN(0x8); - } >iram0_9_seg :iram0_9_phdr - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_dram0_bss_start) - LONG(_dram0_bss_end) - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram0_seg :sram0_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram0_seg :sram0_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram0_seg :sram0_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _image_ram_end = ABSOLUTE(.); - _end = ALIGN(0x8); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_bss_phdr - - PROVIDE(__stack = 0x64000000); - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/esp32/Kconfig.defconfig b/soc/xtensa/esp32/Kconfig.defconfig index ad442007bd1..ef7deea20f3 100644 --- a/soc/xtensa/esp32/Kconfig.defconfig +++ b/soc/xtensa/esp32/Kconfig.defconfig @@ -12,9 +12,6 @@ config SOC config IRQ_OFFLOAD_INTNUM default 7 -config XTENSA_ASM2 - default y - config MP_NUM_CPUS default 2 diff --git a/soc/xtensa/hifi2_std/Kconfig.defconfig b/soc/xtensa/hifi2_std/Kconfig.defconfig deleted file mode 100644 index 6b6108d13b7..00000000000 --- a/soc/xtensa/hifi2_std/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI2_STD - -config SOC - string - default "hifi2_std" - -config IRQ_OFFLOAD_INTNUM - default 7 - -endif diff --git a/soc/xtensa/hifi2_std/Kconfig.soc b/soc/xtensa/hifi2_std/Kconfig.soc deleted file mode 100644 index 680bfadc0b8..00000000000 --- a/soc/xtensa/hifi2_std/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI2_STD - bool "hifi2_std core" diff --git a/soc/xtensa/hifi2_std/linker.ld b/soc/xtensa/hifi2_std/linker.ld deleted file mode 100644 index ab0ae15d4bc..00000000000 --- a/soc/xtensa/hifi2_std/linker.ld +++ /dev/null @@ -1,621 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram19_seg :sram19_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - dram1_0_seg : org = 0x3FFC0000, len = 0x20000 - dram0_0_seg : org = 0x3FFE0000, len = 0x20000 - iram0_0_seg : org = 0x40000000, len = 0x20000 - srom0_seg : org = 0x50000000, len = 0x300 - srom1_seg : org = 0x50000300, len = 0xFFFD00 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x8 - sram2_seg : org = 0x60000180, len = 0x38 - sram3_seg : org = 0x600001B8, len = 0x8 - sram4_seg : org = 0x600001C0, len = 0x38 - sram5_seg : org = 0x600001F8, len = 0x8 - sram6_seg : org = 0x60000200, len = 0x38 - sram7_seg : org = 0x60000238, len = 0x8 - sram8_seg : org = 0x60000240, len = 0x38 - sram9_seg : org = 0x60000278, len = 0x8 - sram10_seg : org = 0x60000280, len = 0x38 - sram11_seg : org = 0x600002B8, len = 0x8 - sram12_seg : org = 0x600002C0, len = 0x38 - sram13_seg : org = 0x600002F8, len = 0x8 - sram14_seg : org = 0x60000300, len = 0x38 - sram15_seg : org = 0x60000338, len = 0x8 - sram16_seg : org = 0x60000340, len = 0x38 - sram17_seg : org = 0x60000378, len = 0x48 - sram18_seg : org = 0x600003C0, len = 0x40 - sram19_seg : org = 0x60000400, len = 0x3FFFC00 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x3ffbe000, len = 0x2000 -#endif -} - -PHDRS -{ - dram1_0_phdr PT_LOAD; - dram1_0_bss_phdr PT_LOAD; - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram10_phdr PT_LOAD; - sram11_phdr PT_LOAD; - sram12_phdr PT_LOAD; - sram13_phdr PT_LOAD; - sram14_phdr PT_LOAD; - sram15_phdr PT_LOAD; - sram16_phdr PT_LOAD; - sram17_phdr PT_LOAD; - sram18_phdr PT_LOAD; - sram19_phdr PT_LOAD; - sram19_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dram1_start = 0x3ffc0000; -_memmap_mem_dram1_end = 0x3ffe0000; -_memmap_mem_dram0_start = 0x3ffe0000; -_memmap_mem_dram0_end = 0x40000000; -_memmap_mem_iram0_start = 0x40000000; -_memmap_mem_iram0_end = 0x40020000; -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dram1_0_start = 0x3ffc0000; -_memmap_seg_dram1_0_max = 0x3ffe0000; -_memmap_seg_dram0_0_start = 0x3ffe0000; -_memmap_seg_dram0_0_max = 0x40000000; -_memmap_seg_iram0_0_start = 0x40000000; -_memmap_seg_iram0_0_max = 0x40020000; -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x50000300; -_memmap_seg_srom1_start = 0x50000300; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x60000180; -_memmap_seg_sram2_start = 0x60000180; -_memmap_seg_sram2_max = 0x600001b8; -_memmap_seg_sram3_start = 0x600001b8; -_memmap_seg_sram3_max = 0x600001c0; -_memmap_seg_sram4_start = 0x600001c0; -_memmap_seg_sram4_max = 0x600001f8; -_memmap_seg_sram5_start = 0x600001f8; -_memmap_seg_sram5_max = 0x60000200; -_memmap_seg_sram6_start = 0x60000200; -_memmap_seg_sram6_max = 0x60000238; -_memmap_seg_sram7_start = 0x60000238; -_memmap_seg_sram7_max = 0x60000240; -_memmap_seg_sram8_start = 0x60000240; -_memmap_seg_sram8_max = 0x60000278; -_memmap_seg_sram9_start = 0x60000278; -_memmap_seg_sram9_max = 0x60000280; -_memmap_seg_sram10_start = 0x60000280; -_memmap_seg_sram10_max = 0x600002b8; -_memmap_seg_sram11_start = 0x600002b8; -_memmap_seg_sram11_max = 0x600002c0; -_memmap_seg_sram12_start = 0x600002c0; -_memmap_seg_sram12_max = 0x600002f8; -_memmap_seg_sram13_start = 0x600002f8; -_memmap_seg_sram13_max = 0x60000300; -_memmap_seg_sram14_start = 0x60000300; -_memmap_seg_sram14_max = 0x60000338; -_memmap_seg_sram15_start = 0x60000338; -_memmap_seg_sram15_max = 0x60000340; -_memmap_seg_sram16_start = 0x60000340; -_memmap_seg_sram16_max = 0x60000378; -_memmap_seg_sram17_start = 0x60000378; -_memmap_seg_sram17_max = 0x600003c0; -_memmap_seg_sram18_start = 0x600003c0; -_memmap_seg_sram18_max = 0x60000400; -_memmap_seg_sram19_start = 0x60000400; -_memmap_seg_sram19_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x60000000); -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00004420; -_memmap_cacheattr_wt_base = 0x00001120; -_memmap_cacheattr_bp_base = 0x00002220; -_memmap_cacheattr_unused_mask = 0xFFFF000F; -_memmap_cacheattr_wb_trapnull = 0x2222442F; -_memmap_cacheattr_wba_trapnull = 0x2222442F; -_memmap_cacheattr_wbna_trapnull = 0x2222552F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF442F; -_memmap_cacheattr_wt_strict = 0xFFFF112F; -_memmap_cacheattr_bp_strict = 0xFFFF222F; -_memmap_cacheattr_wb_allvalid = 0x22224422; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .dram1.rodata : ALIGN(4) - { - _dram1_rodata_start = ABSOLUTE(.); - *(.dram1.rodata) - _dram1_rodata_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.literal : ALIGN(4) - { - _dram1_literal_start = ABSOLUTE(.); - *(.dram1.literal) - _dram1_literal_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.data : ALIGN(4) - { - _dram1_data_start = ABSOLUTE(.); - *(.dram1.data) - _dram1_data_end = ABSOLUTE(.); - } >dram1_0_seg :dram1_0_phdr - - .dram1.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram1_bss_start = ABSOLUTE(.); - *(.dram1.bss) - . = ALIGN (8); - _dram1_bss_end = ABSOLUTE(.); - _memmap_seg_dram1_0_end = ALIGN(0x8); - } >dram1_0_seg :dram1_0_bss_phdr - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - *(.dram0.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .iram0.literal : ALIGN(4) - { - _iram0_literal_start = ABSOLUTE(.); - *(.iram0.literal) - *(.iram.literal) - *(.iram.text.literal) - _iram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _dram0_bss_start = ABSOLUTE(.); - *(.dram0.bss) - . = ALIGN (8); - _dram0_bss_end = ABSOLUTE(.); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.text) - *(.iram.text) - _iram0_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - } >iram0_0_seg :iram0_0_phdr - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram10_end = ALIGN(0x8); - } >sram10_seg :sram10_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram11_end = ALIGN(0x8); - } >sram11_seg :sram11_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram12_end = ALIGN(0x8); - } >sram12_seg :sram12_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram13_end = ALIGN(0x8); - } >sram13_seg :sram13_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram14_end = ALIGN(0x8); - } >sram14_seg :sram14_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram15_end = ALIGN(0x8); - } >sram15_seg :sram15_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram16_end = ALIGN(0x8); - } >sram16_seg :sram16_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram17_end = ALIGN(0x8); - } >sram17_seg :sram17_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram18_end = ALIGN(0x8); - } >sram18_seg :sram18_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_dram1_bss_start) - LONG(_dram1_bss_end) - LONG(_dram0_bss_start) - LONG(_dram0_bss_end) - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram19_seg :sram19_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram19_seg :sram19_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram19_seg :sram19_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram19_end = ALIGN(0x8); - } >sram19_seg :sram19_bss_phdr - PROVIDE(__stack = 0x64000000); - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/hifi3_bd5/Kconfig.defconfig b/soc/xtensa/hifi3_bd5/Kconfig.defconfig deleted file mode 100644 index bf456379ddd..00000000000 --- a/soc/xtensa/hifi3_bd5/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI3_BD5 - -config SOC - string - default "hifi3_bd5" - -config IRQ_OFFLOAD_INTNUM - default 13 - -endif diff --git a/soc/xtensa/hifi3_bd5/Kconfig.soc b/soc/xtensa/hifi3_bd5/Kconfig.soc deleted file mode 100644 index b92d3b366da..00000000000 --- a/soc/xtensa/hifi3_bd5/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI3_BD5 - bool "hifi3_bd5 core" diff --git a/soc/xtensa/hifi3_bd5/linker.ld b/soc/xtensa/hifi3_bd5/linker.ld deleted file mode 100644 index 9fdc38bcb7f..00000000000 --- a/soc/xtensa/hifi3_bd5/linker.ld +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram9_seg :sram9_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - srom0_seg : org = 0x50000000, len = 0x2E0 - srom1_seg : org = 0x500002E0, len = 0xFFFD20 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x4 - sram2_seg : org = 0x6000017C, len = 0x1C - sram3_seg : org = 0x60000198, len = 0x4 - sram4_seg : org = 0x6000019C, len = 0x1C - sram5_seg : org = 0x600001B8, len = 0x4 - sram6_seg : org = 0x600001BC, len = 0x1C - sram7_seg : org = 0x600001D8, len = 0x4 - sram8_seg : org = 0x600001DC, len = 0x1C - sram9_seg : org = 0x600001F8, len = 0x3FFFE08 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x4fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram9_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x500002e0; -_memmap_seg_srom1_start = 0x500002e0; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x6000017c; -_memmap_seg_sram2_start = 0x6000017c; -_memmap_seg_sram2_max = 0x60000198; -_memmap_seg_sram3_start = 0x60000198; -_memmap_seg_sram3_max = 0x6000019c; -_memmap_seg_sram4_start = 0x6000019c; -_memmap_seg_sram4_max = 0x600001b8; -_memmap_seg_sram5_start = 0x600001b8; -_memmap_seg_sram5_max = 0x600001bc; -_memmap_seg_sram6_start = 0x600001bc; -_memmap_seg_sram6_max = 0x600001d8; -_memmap_seg_sram7_start = 0x600001d8; -_memmap_seg_sram7_max = 0x600001dc; -_memmap_seg_sram8_start = 0x600001dc; -_memmap_seg_sram8_max = 0x600001f8; -_memmap_seg_sram9_start = 0x600001f8; -_memmap_seg_sram9_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x60000000); -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00004400; -_memmap_cacheattr_wt_base = 0x00001100; -_memmap_cacheattr_bp_base = 0x00002200; -_memmap_cacheattr_unused_mask = 0xFFFF00FF; -_memmap_cacheattr_wb_trapnull = 0x2222442F; -_memmap_cacheattr_wba_trapnull = 0x2222442F; -_memmap_cacheattr_wbna_trapnull = 0x2222552F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF44FF; -_memmap_cacheattr_wt_strict = 0xFFFF11FF; -_memmap_cacheattr_bp_strict = 0xFFFF22FF; -_memmap_cacheattr_wb_allvalid = 0x22224422; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - - .sram.text : ALIGN(4) - { - _sram_text_start = ABSOLUTE(.); - *(.sram.literal .sram.text) - _sram_text_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sram9_seg :sram9_phdr - _image_text_end = .; - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram9_seg :sram9_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_bss_phdr - __stack = 0x64000000; - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/hifi3_bd5_call0/Kconfig.defconfig b/soc/xtensa/hifi3_bd5_call0/Kconfig.defconfig deleted file mode 100644 index 99d4c7d3150..00000000000 --- a/soc/xtensa/hifi3_bd5_call0/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI3_BD5_CALL0 - -config SOC - string - default "hifi3_bd5_call0" - -config IRQ_OFFLOAD_INTNUM - default 13 - -endif diff --git a/soc/xtensa/hifi3_bd5_call0/Kconfig.soc b/soc/xtensa/hifi3_bd5_call0/Kconfig.soc deleted file mode 100644 index 9d8a8869650..00000000000 --- a/soc/xtensa/hifi3_bd5_call0/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI3_BD5_CALL0 - bool "hifi3_bd5_call0 (hifi3_bd5 core with call0 ABI and 3 additional SW IRQs)" diff --git a/soc/xtensa/hifi3_bd5_call0/linker.ld b/soc/xtensa/hifi3_bd5_call0/linker.ld deleted file mode 100644 index 9fdc38bcb7f..00000000000 --- a/soc/xtensa/hifi3_bd5_call0/linker.ld +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram9_seg :sram9_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - srom0_seg : org = 0x50000000, len = 0x2E0 - srom1_seg : org = 0x500002E0, len = 0xFFFD20 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x4 - sram2_seg : org = 0x6000017C, len = 0x1C - sram3_seg : org = 0x60000198, len = 0x4 - sram4_seg : org = 0x6000019C, len = 0x1C - sram5_seg : org = 0x600001B8, len = 0x4 - sram6_seg : org = 0x600001BC, len = 0x1C - sram7_seg : org = 0x600001D8, len = 0x4 - sram8_seg : org = 0x600001DC, len = 0x1C - sram9_seg : org = 0x600001F8, len = 0x3FFFE08 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x4fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram9_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x51000000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x64000000; - -/* Memory segment boundary addresses: */ -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x500002e0; -_memmap_seg_srom1_start = 0x500002e0; -_memmap_seg_srom1_max = 0x51000000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x6000017c; -_memmap_seg_sram2_start = 0x6000017c; -_memmap_seg_sram2_max = 0x60000198; -_memmap_seg_sram3_start = 0x60000198; -_memmap_seg_sram3_max = 0x6000019c; -_memmap_seg_sram4_start = 0x6000019c; -_memmap_seg_sram4_max = 0x600001b8; -_memmap_seg_sram5_start = 0x600001b8; -_memmap_seg_sram5_max = 0x600001bc; -_memmap_seg_sram6_start = 0x600001bc; -_memmap_seg_sram6_max = 0x600001d8; -_memmap_seg_sram7_start = 0x600001d8; -_memmap_seg_sram7_max = 0x600001dc; -_memmap_seg_sram8_start = 0x600001dc; -_memmap_seg_sram8_max = 0x600001f8; -_memmap_seg_sram9_start = 0x600001f8; -_memmap_seg_sram9_max = 0x64000000; - -_rom_store_table = 0; -PROVIDE(_memmap_vecbase_reset = 0x60000000); -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00004400; -_memmap_cacheattr_wt_base = 0x00001100; -_memmap_cacheattr_bp_base = 0x00002200; -_memmap_cacheattr_unused_mask = 0xFFFF00FF; -_memmap_cacheattr_wb_trapnull = 0x2222442F; -_memmap_cacheattr_wba_trapnull = 0x2222442F; -_memmap_cacheattr_wbna_trapnull = 0x2222552F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF44FF; -_memmap_cacheattr_wt_strict = 0xFFFF11FF; -_memmap_cacheattr_bp_strict = 0xFFFF22FF; -_memmap_cacheattr_wb_allvalid = 0x22224422; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); 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- *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram9_seg :sram9_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_bss_phdr - __stack = 0x64000000; - _heap_sentry = 0x64000000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/hifi4_bd7/Kconfig.defconfig b/soc/xtensa/hifi4_bd7/Kconfig.defconfig deleted file mode 100644 index a13dd1b9597..00000000000 --- a/soc/xtensa/hifi4_bd7/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI4_BD7 - -config SOC - string - default "hifi4_bd7" - -config IRQ_OFFLOAD_INTNUM - default 4 - -endif diff --git a/soc/xtensa/hifi4_bd7/Kconfig.soc b/soc/xtensa/hifi4_bd7/Kconfig.soc deleted file mode 100644 index 9c9753fb337..00000000000 --- a/soc/xtensa/hifi4_bd7/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI4_BD7 - bool "hifi4_bd7 core" diff --git a/soc/xtensa/hifi4_bd7/linker.ld b/soc/xtensa/hifi4_bd7/linker.ld deleted file mode 100644 index 3ba732c0943..00000000000 --- a/soc/xtensa/hifi4_bd7/linker.ld +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram13_seg :sram13_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - srom0_seg : org = 0x50000000, len = 0x300 - srom1_seg : org = 0x50000300, len = 0x1FD00 - sram0_seg : org = 0x60000000, len = 0x178 - sram1_seg : org = 0x60000178, len = 0x8 - sram2_seg : org = 0x60000180, len = 0x38 - sram3_seg : org = 0x600001B8, len = 0x8 - sram4_seg : org = 0x600001C0, len = 0x38 - sram5_seg : org = 0x600001F8, len = 0x8 - sram6_seg : org = 0x60000200, len = 0x38 - sram7_seg : org = 0x60000238, len = 0x8 - sram8_seg : org = 0x60000240, len = 0x38 - sram9_seg : org = 0x60000278, len = 0x8 - sram10_seg : org = 0x60000280, len = 0x38 - sram11_seg : org = 0x600002B8, len = 0x48 - sram12_seg : org = 0x60000300, len = 0x40 - sram13_seg : org = 0x60000340, len = 0x3FFCC0 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x4fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - srom0_phdr PT_LOAD; - srom1_phdr PT_LOAD; - sram0_phdr PT_LOAD; - sram1_phdr PT_LOAD; - sram2_phdr PT_LOAD; - sram3_phdr PT_LOAD; - sram4_phdr PT_LOAD; - sram5_phdr PT_LOAD; - sram6_phdr PT_LOAD; - sram7_phdr PT_LOAD; - sram8_phdr PT_LOAD; - sram9_phdr PT_LOAD; - sram10_phdr PT_LOAD; - sram11_phdr PT_LOAD; - sram12_phdr PT_LOAD; - sram13_phdr PT_LOAD; - sram13_bss_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_srom_start = 0x50000000; -_memmap_mem_srom_end = 0x50020000; -_memmap_mem_sram_start = 0x60000000; -_memmap_mem_sram_end = 0x60400000; - -/* Memory segment boundary addresses: */ -_memmap_seg_srom0_start = 0x50000000; -_memmap_seg_srom0_max = 0x50000300; -_memmap_seg_srom1_start = 0x50000300; -_memmap_seg_srom1_max = 0x50020000; -_memmap_seg_sram0_start = 0x60000000; -_memmap_seg_sram0_max = 0x60000178; -_memmap_seg_sram1_start = 0x60000178; -_memmap_seg_sram1_max = 0x60000180; -_memmap_seg_sram2_start = 0x60000180; -_memmap_seg_sram2_max = 0x600001b8; -_memmap_seg_sram3_start = 0x600001b8; -_memmap_seg_sram3_max = 0x600001c0; -_memmap_seg_sram4_start = 0x600001c0; -_memmap_seg_sram4_max = 0x600001f8; -_memmap_seg_sram5_start = 0x600001f8; -_memmap_seg_sram5_max = 0x60000200; -_memmap_seg_sram6_start = 0x60000200; -_memmap_seg_sram6_max = 0x60000238; -_memmap_seg_sram7_start = 0x60000238; -_memmap_seg_sram7_max = 0x60000240; -_memmap_seg_sram8_start = 0x60000240; -_memmap_seg_sram8_max = 0x60000278; -_memmap_seg_sram9_start = 0x60000278; -_memmap_seg_sram9_max = 0x60000280; -_memmap_seg_sram10_start = 0x60000280; -_memmap_seg_sram10_max = 0x600002b8; -_memmap_seg_sram11_start = 0x600002b8; -_memmap_seg_sram11_max = 0x60000300; -_memmap_seg_sram12_start = 0x60000300; -_memmap_seg_sram12_max = 0x60000340; -_memmap_seg_sram13_start = 0x60000340; -_memmap_seg_sram13_max = 0x60400000; - -_rom_store_table = 0; -PROVIDE(_memmap_reset_vector = 0x50000000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00004400; -_memmap_cacheattr_wt_base = 0x00001100; -_memmap_cacheattr_bp_base = 0x00002200; -_memmap_cacheattr_unused_mask = 0xFFFF00FF; -_memmap_cacheattr_wb_trapnull = 0x2222442F; -_memmap_cacheattr_wba_trapnull = 0x2222442F; -_memmap_cacheattr_wbna_trapnull = 0x2222552F; -_memmap_cacheattr_wt_trapnull = 0x2222112F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF44FF; -_memmap_cacheattr_wt_strict = 0xFFFF11FF; -_memmap_cacheattr_bp_strict = 0xFFFF22FF; -_memmap_cacheattr_wb_allvalid = 0x22224422; -_memmap_cacheattr_wt_allvalid = 0x22221122; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_srom0_end = ALIGN(0x8); - } >srom0_seg :srom0_phdr - - .srom.rodata : ALIGN(4) - { - _srom_rodata_start = ABSOLUTE(.); - *(.srom.rodata) - _srom_rodata_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .srom.text : ALIGN(4) - { - _srom_text_start = ABSOLUTE(.); - *(.srom.literal .srom.text) - _srom_text_end = ABSOLUTE(.); - _memmap_seg_srom1_end = ALIGN(0x8); - _image_rom_end = ABSOLUTE(.); - } >srom1_seg :srom1_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - _memmap_seg_sram0_end = ALIGN(0x8); - } >sram0_seg :sram0_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram1_end = ALIGN(0x8); - } >sram1_seg :sram1_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram2_end = ALIGN(0x8); - } >sram2_seg :sram2_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram3_end = ALIGN(0x8); - } >sram3_seg :sram3_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram4_end = ALIGN(0x8); - } >sram4_seg :sram4_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram5_end = ALIGN(0x8); - } >sram5_seg :sram5_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - _memmap_seg_sram6_end = ALIGN(0x8); - } >sram6_seg :sram6_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram7_end = ALIGN(0x8); - } >sram7_seg :sram7_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram8_end = ALIGN(0x8); - } >sram8_seg :sram8_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram9_end = ALIGN(0x8); - } >sram9_seg :sram9_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram10_end = ALIGN(0x8); - } >sram10_seg :sram10_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_sram11_end = ALIGN(0x8); - } >sram11_seg :sram11_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_sram12_end = ALIGN(0x8); - } >sram12_seg :sram12_phdr - - .sram.rodata : ALIGN(4) - { - _image_ram_start = ABSOLUTE(.); - _sram_rodata_start = ABSOLUTE(.); - *(.sram.rodata) - _sram_rodata_end = ABSOLUTE(.); - } >sram13_seg :sram13_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 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- *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >sram13_seg :sram13_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >sram13_seg :sram13_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >sram13_seg :sram13_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.sram.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_sram13_end = ALIGN(0x8); - } >sram13_seg :sram13_bss_phdr - __stack = 0x60400000; - _heap_sentry = 0x60400000; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/hifi_mini/Kconfig.defconfig b/soc/xtensa/hifi_mini/Kconfig.defconfig deleted file mode 100644 index 141f5e7c9e6..00000000000 --- a/soc/xtensa/hifi_mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI_MINI - -config SOC - string - default "hifi_mini" - -config IRQ_OFFLOAD_INTNUM - default 13 - -endif diff --git a/soc/xtensa/hifi_mini/Kconfig.soc b/soc/xtensa/hifi_mini/Kconfig.soc deleted file mode 100644 index 6c8ee15adea..00000000000 --- a/soc/xtensa/hifi_mini/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI_MINI - bool "hifi_mini core" diff --git a/soc/xtensa/hifi_mini/linker.ld b/soc/xtensa/hifi_mini/linker.ld deleted file mode 100644 index 729fddbd8d4..00000000000 --- a/soc/xtensa/hifi_mini/linker.ld +++ /dev/null @@ -1,369 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr -#define ROMABLE_REGION iram0_7_seg :iram0_7_phdr - -MEMORY -{ - dram0_0_seg : org = 0x60000000, len = 0x20000 - iram0_0_seg : org = 0x60020000, len = 0x2E0 - iram0_1_seg : org = 0x600202E0, len = 0x4 - iram0_2_seg : org = 0x600202E4, len = 0x1C - iram0_3_seg : org = 0x60020300, len = 0x4 - iram0_4_seg : org = 0x60020304, len = 0x1C - iram0_5_seg : org = 0x60020320, len = 0x4 - iram0_6_seg : org = 0x60020324, len = 0x1C - iram0_7_seg : org = 0x60020340, len = 0x1FCC0 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x5fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - iram0_1_phdr PT_LOAD; - iram0_2_phdr PT_LOAD; - iram0_3_phdr PT_LOAD; - iram0_4_phdr PT_LOAD; - iram0_5_phdr PT_LOAD; - iram0_6_phdr PT_LOAD; - iram0_7_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dram0_start = 0x60000000; -_memmap_mem_dram0_end = 0x60020000; -_memmap_mem_iram0_start = 0x60020000; -_memmap_mem_iram0_end = 0x60040000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dram0_0_start = 0x60000000; -_memmap_seg_dram0_0_max = 0x60020000; -_memmap_seg_iram0_0_start = 0x60020000; -_memmap_seg_iram0_0_max = 0x600202e0; -_memmap_seg_iram0_1_start = 0x600202e0; -_memmap_seg_iram0_1_max = 0x600202e4; -_memmap_seg_iram0_2_start = 0x600202e4; -_memmap_seg_iram0_2_max = 0x60020300; -_memmap_seg_iram0_3_start = 0x60020300; -_memmap_seg_iram0_3_max = 0x60020304; -_memmap_seg_iram0_4_start = 0x60020304; -_memmap_seg_iram0_4_max = 0x60020320; -_memmap_seg_iram0_5_start = 0x60020320; -_memmap_seg_iram0_5_max = 0x60020324; -_memmap_seg_iram0_6_start = 0x60020324; -_memmap_seg_iram0_6_max = 0x60020340; -_memmap_seg_iram0_7_start = 0x60020340; -_memmap_seg_iram0_7_max = 0x60040000; - -_rom_store_table = 0; -PROVIDE(_memmap_reset_vector = 0x60020000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00001000; -_memmap_cacheattr_wt_base = 0x00001000; -_memmap_cacheattr_bp_base = 0x00002000; -_memmap_cacheattr_unused_mask = 0xFFFF0FFF; -_memmap_cacheattr_wb_trapnull = 0x2222122F; -_memmap_cacheattr_wba_trapnull = 0x2222122F; -_memmap_cacheattr_wbna_trapnull = 0x2222122F; -_memmap_cacheattr_wt_trapnull = 0x2222122F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF1FFF; -_memmap_cacheattr_wt_strict = 0xFFFF1FFF; -_memmap_cacheattr_bp_strict = 0xFFFF2FFF; -_memmap_cacheattr_wb_allvalid = 0x22221222; -_memmap_cacheattr_wt_allvalid = 0x22221222; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); - -SECTIONS -{ - -#include - - .dram0.rodata : ALIGN(4) - { - _dram0_rodata_start = ABSOLUTE(.); - _image_ram_start = ABSOLUTE(.); - *(.dram0.rodata) - *(.dram.rodata) - _dram0_rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - -#include - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.literal : ALIGN(4) - { - _dram0_literal_start = ABSOLUTE(.); - *(.dram0.literal) - *(.dram.literal) - _dram0_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .dram0.data : ALIGN(4) - { - _dram0_data_start = ABSOLUTE(.); - *(.dram0.data) - *(.dram.data) - _dram0_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .sram.data : ALIGN(4) - { - _sram_data_start = ABSOLUTE(.); - *(.sram.data) - _sram_data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - - .noinit : ALIGN(4) - { - *(.noinit) - *(.noinit.*) - } >dram0_0_seg :dram0_0_phdr - - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - } >dram0_0_seg :dram0_0_phdr - -#include - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - *(.dram0.bss) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - _end = ALIGN(0x8); - _image_ram_end = ABSOLUTE(.); - PROVIDE(end = ALIGN(0x8)); - _stack_sentry = ALIGN(0x8); - _memmap_seg_dram0_0_end = ALIGN(0x8); - } >dram0_0_seg :dram0_0_bss_phdr - __stack = 0x60020000; - _heap_sentry = 0x60020000; - - .ResetVector.text : ALIGN(4) - { - _image_rom_start = ABSOLUTE(.); - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_0_end = ALIGN(0x8); - } >iram0_0_seg :iram0_0_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_1_end = ALIGN(0x8); - } >iram0_1_seg :iram0_1_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_2_end = ALIGN(0x8); - } >iram0_2_seg :iram0_2_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_3_end = ALIGN(0x8); - } >iram0_3_seg :iram0_3_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_4_end = ALIGN(0x8); - } >iram0_4_seg :iram0_4_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - _memmap_seg_iram0_5_end = ALIGN(0x8); - } >iram0_5_seg :iram0_5_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - _memmap_seg_iram0_6_end = ALIGN(0x8); - } >iram0_6_seg :iram0_6_phdr - - .iram0.text : ALIGN(4) - { - _iram0_text_start = ABSOLUTE(.); - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - _iram0_text_end = ABSOLUTE(.); - _image_rom_end = ABSOLUTE(.); - } >iram0_7_seg :iram0_7_phdr - - _image_text_start = ALIGN(4); - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >iram0_7_seg :iram0_7_phdr - _image_text_end = .; - .comment 0 : { *(.comment) } - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - .debug_ranges 0 : { *(.debug_ranges) } - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .debug.xt.callgraph 0 : - { - KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) - } -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif -} diff --git a/soc/xtensa/hifi_mini_4swIrq/Kconfig.defconfig b/soc/xtensa/hifi_mini_4swIrq/Kconfig.defconfig deleted file mode 100644 index ae5ae598c91..00000000000 --- a/soc/xtensa/hifi_mini_4swIrq/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Kconfig - XTENSA board configuration -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_HIFI_MINI_4SWIRQ - -config SOC - string - default "hifi_mini_4swIrq" - -config IRQ_OFFLOAD_INTNUM - default 1 - -endif diff --git a/soc/xtensa/hifi_mini_4swIrq/Kconfig.soc b/soc/xtensa/hifi_mini_4swIrq/Kconfig.soc deleted file mode 100644 index dad109c49eb..00000000000 --- a/soc/xtensa/hifi_mini_4swIrq/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_HIFI_MINI_4SWIRQ - bool "hifi_mini_4swIrq (hifi_mini core with 4 additional SW IRQs)" diff --git a/soc/xtensa/hifi_mini_4swIrq/linker.ld b/soc/xtensa/hifi_mini_4swIrq/linker.ld deleted file mode 100644 index 811614d6af9..00000000000 --- a/soc/xtensa/hifi_mini_4swIrq/linker.ld +++ /dev/null @@ -1,369 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#define _LINKER -#define _ASMLANGUAGE - -#include -#include - -#include -#include - -#define RAMABLE_REGION sram0_0_seg :sram0_0_phdr -#define ROMABLE_REGION srom1_seg :srom1_phdr - -MEMORY -{ - dram0_0_seg : org = 0x60000000, len = 0x20000 - iram0_0_seg : org = 0x60020000, len = 0x2E0 - iram0_1_seg : org = 0x600202E0, len = 0x4 - iram0_2_seg : org = 0x600202E4, len = 0x1C - iram0_3_seg : org = 0x60020300, len = 0x4 - iram0_4_seg : org = 0x60020304, len = 0x1C - iram0_5_seg : org = 0x60020320, len = 0x4 - iram0_6_seg : org = 0x60020324, len = 0x1C - iram0_7_seg : org = 0x60020340, len = 0x1FCC0 -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST : org = 0x5fffe000, len = 0x2000 -#endif -} - -PHDRS -{ - dram0_0_phdr PT_LOAD; - dram0_0_bss_phdr PT_LOAD; - iram0_0_phdr PT_LOAD; - iram0_1_phdr PT_LOAD; - iram0_2_phdr PT_LOAD; - iram0_3_phdr PT_LOAD; - iram0_4_phdr PT_LOAD; - iram0_5_phdr PT_LOAD; - iram0_6_phdr PT_LOAD; - iram0_7_phdr PT_LOAD; -} - - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -/* Memory boundary addresses: */ -_memmap_mem_dram0_start = 0x60000000; -_memmap_mem_dram0_end = 0x60020000; -_memmap_mem_iram0_start = 0x60020000; -_memmap_mem_iram0_end = 0x60040000; - -/* Memory segment boundary addresses: */ -_memmap_seg_dram0_0_start = 0x60000000; -_memmap_seg_dram0_0_max = 0x60020000; -_memmap_seg_iram0_0_start = 0x60020000; -_memmap_seg_iram0_0_max = 0x600202e0; -_memmap_seg_iram0_1_start = 0x600202e0; -_memmap_seg_iram0_1_max = 0x600202e4; -_memmap_seg_iram0_2_start = 0x600202e4; -_memmap_seg_iram0_2_max = 0x60020300; -_memmap_seg_iram0_3_start = 0x60020300; -_memmap_seg_iram0_3_max = 0x60020304; -_memmap_seg_iram0_4_start = 0x60020304; -_memmap_seg_iram0_4_max = 0x60020320; -_memmap_seg_iram0_5_start = 0x60020320; -_memmap_seg_iram0_5_max = 0x60020324; -_memmap_seg_iram0_6_start = 0x60020324; -_memmap_seg_iram0_6_max = 0x60020340; -_memmap_seg_iram0_7_start = 0x60020340; -_memmap_seg_iram0_7_max = 0x60040000; - -_rom_store_table = 0; -PROVIDE(_memmap_reset_vector = 0x60020000); -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x00001000; -_memmap_cacheattr_wt_base = 0x00001000; -_memmap_cacheattr_bp_base = 0x00002000; -_memmap_cacheattr_unused_mask = 0xFFFF0FFF; -_memmap_cacheattr_wb_trapnull = 0x2222122F; -_memmap_cacheattr_wba_trapnull = 0x2222122F; -_memmap_cacheattr_wbna_trapnull = 0x2222122F; -_memmap_cacheattr_wt_trapnull = 0x2222122F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0xFFFF1FFF; -_memmap_cacheattr_wt_strict = 0xFFFF1FFF; -_memmap_cacheattr_bp_strict = 0xFFFF2FFF; -_memmap_cacheattr_wb_allvalid = 0x22221222; -_memmap_cacheattr_wt_allvalid = 0x22221222; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 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