From 6351d6671d43356a7262998780f676c25901e1d2 Mon Sep 17 00:00:00 2001 From: Tomasz Bursztyka Date: Fri, 27 Nov 2015 14:23:02 +0100 Subject: [PATCH] quark_se: Exposing only one gpio controller and fixing his bits There is no secondary GPIO controller on such SoC. Plus, the unique controller controls at least 28 pins (if not 32, so I set 32), as verified on boards. Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3 Signed-off-by: Tomasz Bursztyka --- arch/x86/platforms/quark_se/Kconfig | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/x86/platforms/quark_se/Kconfig b/arch/x86/platforms/quark_se/Kconfig index 2fdaa0adf0e..4a5e39b0dcf 100644 --- a/arch/x86/platforms/quark_se/Kconfig +++ b/arch/x86/platforms/quark_se/Kconfig @@ -85,16 +85,7 @@ config GPIO_DW_0_BASE_ADDR config GPIO_DW_0_IRQ default 8 config GPIO_DW_0_BITS - default 8 - -config GPIO_DW_1 - def_bool y -config GPIO_DW_1_BASE_ADDR - default 0xb0001700 -config GPIO_DW_1_IRQ - default 8 -config GPIO_DW_0_BITS - default 8 + default 32 endif if I2C