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drivers/uart: Use dts to set uart options for ns16550 driver

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Fix the ns16550 uart driver and relevant SoCs accordingly.
All generic settings are now DTS based.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2018-03-05 14:38:50 +01:00 • committed by Anas Nashif
commit 61ef30d10e
23 changed files with 93 additions and 168 deletions
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13
arch/arc/soc/quark_se_c1000_ss/soc.h
View file

@ -158,19 +158,6 @@
/* /*
* UART * UART
*/ */
#define UART_IRQ_FLAGS 0
#define UART_NS16550_PORT_0_BASE_ADDR 0xB0002000
#define UART_NS16550_PORT_0_IRQ 41
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_0_INT_MASK 0x460
#define UART_NS16550_PORT_1_BASE_ADDR 0xB0002400
#define UART_NS16550_PORT_1_IRQ 42
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_1_INT_MASK 0x464
#define CONFIG_UART_QMSI_0_IRQ_FLAGS 0 #define CONFIG_UART_QMSI_0_IRQ_FLAGS 0
#define CONFIG_UART_QMSI_1_IRQ_FLAGS 0 #define CONFIG_UART_QMSI_1_IRQ_FLAGS 0

23
arch/arc/soc/quark_se_c1000_ss/soc_config.c
View file

@ -42,26 +42,3 @@ DEVICE_INIT(ipm_console, "ipm_console", ipm_console_sender_init,
#endif /* CONFIG_IPM_CONSOLE_SENDER */ #endif /* CONFIG_IPM_CONSOLE_SENDER */
#endif /* CONFIG_IPM_QUARK_SE */ #endif /* CONFIG_IPM_QUARK_SE */
#ifdef CONFIG_UART_NS16550
static int uart_ns16550_init(struct device *dev)
{
ARG_UNUSED(dev);
#ifdef CONFIG_UART_NS16550_PORT_0
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK),
INT_ENABLE_ARC_BIT_POS);
#endif /* CONFIG_UART_NS16550_PORT_0 */
#ifdef CONFIG_UART_NS16550_PORT_1
sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK),
INT_ENABLE_ARC_BIT_POS);
#endif /* CONFIG_UART_NS16550_PORT_1 */
return 0;
}
SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* CONFIG_UART_NS16550 */

22
arch/arc/soc/snps_emsk/dts.fixup
View file

@ -9,32 +9,28 @@
/* /*
* UART configuration * UART configuration
* BASE_ADDR, IRQ, CLK_FREQ are fixed, no need to fixup
*/ */
#define UART_NS16550_PORT_0_BASE_ADDR NS16550_F0008000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_F0008000_BASE_ADDRESS
#define UART_NS16550_PORT_0_IRQ NS16550_F0008000_IRQ_0 #define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_F0008000_IRQ_0
#define UART_NS16550_PORT_0_CLK_FREQ NS16550_F0008000_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_F0008000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL #define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_F0008000_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_F0008000_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_F0009000_BASE_ADDRESS
#define UART_NS16550_PORT_1_BASE_ADDR NS16550_F0009000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_F0009000_IRQ_0
#define UART_NS16550_PORT_1_IRQ NS16550_F0009000_IRQ_0 #define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_F0009000_CLOCK_FREQUENCY
#define UART_NS16550_PORT_1_CLK_FREQ NS16550_F0009000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_F0009000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_F0009000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_F0009000_LABEL #define CONFIG_UART_NS16550_PORT_1_NAME NS16550_F0009000_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_F0009000_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_F0009000_IRQ_0_PRIORITY
#define UART_NS16550_PORT_2_BASE_ADDR NS16550_F000A000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_2_BASE_ADDR NS16550_F000A000_BASE_ADDRESS
#define UART_NS16550_PORT_2_IRQ NS16550_F000A000_IRQ_0 #define CONFIG_UART_NS16550_PORT_2_IRQ NS16550_F000A000_IRQ_0
#define UART_NS16550_PORT_2_CLK_FREQ NS16550_F000A000_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_2_CLK_FREQ NS16550_F000A000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE NS16550_F000A000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_2_BAUD_RATE NS16550_F000A000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_2_NAME NS16550_F000A000_LABEL #define CONFIG_UART_NS16550_PORT_2_NAME NS16550_F000A000_LABEL
#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI NS16550_F000A000_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_2_IRQ_PRI NS16550_F000A000_IRQ_0_PRIORITY
#define UART_IRQ_FLAGS 0
/* /*
* I2C configuration * I2C configuration
*/ */

26
arch/arc/soc/snps_emsk/soc.h
View file

@ -54,6 +54,12 @@
#define INT_ENABLE_ARC ~(0x00000001 << 8) #define INT_ENABLE_ARC ~(0x00000001 << 8)
#define INT_ENABLE_ARC_BIT_POS (8) #define INT_ENABLE_ARC_BIT_POS (8)
/*
* UARTs: UART0 & UART1 & UART2
*/
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
#define CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
#ifndef CONFIG_HAS_DTS #ifndef CONFIG_HAS_DTS
/* I2C */ /* I2C */
@ -103,20 +109,6 @@
* CS5 SPI-Flash (onboard) * CS5 SPI-Flash (onboard)
*/ */
/*
* UARTs: UART0 & UART1 & UART2
*/
#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_NS16550_PORT_2_BASE_ADDR 0xF000A000
#define UART_NS16550_PORT_2_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
#define UART_IRQ_FLAGS 0 /* Default */
/** /**
* Peripheral Interrupt Connection Configurations * Peripheral Interrupt Connection Configurations
*/ */
@ -126,18 +118,12 @@
#define CONFIG_I2C_1_IRQ 26 #define CONFIG_I2C_1_IRQ 26
#define SPI_DW_PORT_0_IRQ 27 #define SPI_DW_PORT_0_IRQ 27
#define SPI_DW_PORT_1_IRQ 28 #define SPI_DW_PORT_1_IRQ 28
#define UART_NS16550_PORT_0_IRQ 29
#define UART_NS16550_PORT_1_IRQ 30
#define UART_NS16550_PORT_2_IRQ 31
#else /* CONFIG_BOARD_EM_STARTERKIT_R23 */ #else /* CONFIG_BOARD_EM_STARTERKIT_R23 */
#define GPIO_DW_0_IRQ 22 #define GPIO_DW_0_IRQ 22
#define CONFIG_I2C_0_IRQ 23 #define CONFIG_I2C_0_IRQ 23
#define CONFIG_I2C_1_IRQ 24 #define CONFIG_I2C_1_IRQ 24
#define SPI_DW_PORT_0_IRQ 25 #define SPI_DW_PORT_0_IRQ 25
#define SPI_DW_PORT_1_IRQ 26 #define SPI_DW_PORT_1_IRQ 26
#define UART_NS16550_PORT_0_IRQ 27
#define UART_NS16550_PORT_1_IRQ 28
#define UART_NS16550_PORT_2_IRQ 29
#endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */ #endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */
#define GPIO_DW_1_IRQ 0 /* can't interrupt */ #define GPIO_DW_1_IRQ 0 /* can't interrupt */

8
arch/arc/soc/snps_emsk/soc_config.c
View file

@ -19,12 +19,12 @@ static int uart_ns16550_init(struct device *dev)
* send the UART the command to clear the interrupt * send the UART the command to clear the interrupt
*/ */
#ifdef CONFIG_UART_NS16550_PORT_0 #ifdef CONFIG_UART_NS16550_PORT_0
sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4); sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x4);
sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10); sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x10);
#endif /* CONFIG_UART_NS16550_PORT_0 */ #endif /* CONFIG_UART_NS16550_PORT_0 */
#ifdef CONFIG_UART_NS16550_PORT_1 #ifdef CONFIG_UART_NS16550_PORT_1
sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4); sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x4);
sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10); sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x10);
#endif /* CONFIG_UART_NS16550_PORT_1 */ #endif /* CONFIG_UART_NS16550_PORT_1 */
return 0; return 0;

6
arch/nios2/soc/nios2f-zephyr/soc.h
View file

@ -10,8 +10,8 @@
#include <system.h> #include <system.h>
#define UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE
#define UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ #define CONFIG_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ
#define UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ #define CONFIG_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ
#endif #endif

8
arch/riscv32/soc/pulpino/soc.h
View file

@ -59,9 +59,11 @@
#define SOC_ERET eret #define SOC_ERET eret
/* UART configuration */ /* UART configuration */
#define UART_NS16550_PORT_0_BASE_ADDR 0x1A100000 #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR 0x1A100000
#define UART_NS16550_PORT_0_CLK_FREQ 2500000 #define CONFIG_UART_NS16550_PORT_0_CLK_FREQ 2500000
#define UART_NS16550_PORT_0_IRQ PULP_UART_0_IRQ #define CONFIG_UART_NS16550_PORT_0_IRQ PULP_UART_0_IRQ
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI 0
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0
/* GPIO configuration */ /* GPIO configuration */
#define PULP_GPIO_0_BASE 0x1A101000 #define PULP_GPIO_0_BASE 0x1A101000

6
arch/x86/soc/atom/Kconfig.defconfig
View file

@ -28,9 +28,6 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_IRQ_PRI
default 3
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
@ -41,9 +38,6 @@ config UART_NS16550_PORT_1
if UART_NS16550_PORT_1 if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_IRQ_PRI
default 3
config UART_NS16550_PORT_1_OPTIONS config UART_NS16550_PORT_1_OPTIONS
default 0 default 0

20
arch/x86/soc/atom/dts.fixup
View file

@ -1,12 +1,20 @@
/* SoC level DTS fixup file */ /* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_F0009000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_000003F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_000003F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_000003F8_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_000003F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_000003F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_000003F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_000003F8_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_F0009000_LABEL #define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_000002F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_000002F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME NS16550_000002F8_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_000002F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_000002F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS NS16550_000002F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_000002F8_CLOCK_FREQUENCY
#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS

13
arch/x86/soc/atom/soc.h
View file

@ -29,19 +29,6 @@
*/ */
#define UART_NS16550_ACCESS_IOPORT #define UART_NS16550_ACCESS_IOPORT
#define UART_NS16550_PORT_0_BASE_ADDR 0x03F8
#define UART_NS16550_PORT_0_IRQ 4
#define UART_NS16550_PORT_0_CLK_FREQ 1843200
#define UART_NS16550_PORT_1_BASE_ADDR 0x02F8
#define UART_NS16550_PORT_1_IRQ 3
#define UART_NS16550_PORT_1_CLK_FREQ 1843200
#ifdef CONFIG_IOAPIC
#include <drivers/ioapic.h>
#define UART_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
#endif /* CONFIG_IOAPIC */
/* PCI definitions */ /* PCI definitions */
/* FIXME: The values below copied from generic ia32 soc, we need to get the /* FIXME: The values below copied from generic ia32 soc, we need to get the

4
arch/x86/soc/ia32/Kconfig.defconfig
View file

@ -28,8 +28,6 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_IRQ_PRI
default 3
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
@ -40,8 +38,6 @@ config UART_NS16550_PORT_1
if UART_NS16550_PORT_1 if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_IRQ_PRI
default 3
config UART_NS16550_PORT_1_OPTIONS config UART_NS16550_PORT_1_OPTIONS
default 0 default 0

20
arch/x86/soc/ia32/dts.fixup
View file

@ -1,12 +1,20 @@
/* SoC level DTS fixup file */ /* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_F0009000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_000003F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_000003F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_000003F8_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_000003F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_000003F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_000003F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_000003F8_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_F0009000_LABEL #define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_000002F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_000002F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME NS16550_000002F8_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_000002F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_000002F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS NS16550_000002F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_000002F8_CLOCK_FREQUENCY
#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS

14
arch/x86/soc/ia32/soc.h
View file

@ -27,20 +27,6 @@
*/ */
#define UART_NS16550_ACCESS_IOPORT #define UART_NS16550_ACCESS_IOPORT
#define UART_NS16550_PORT_0_BASE_ADDR 0x03F8
#define UART_NS16550_PORT_0_IRQ 4
#define UART_NS16550_PORT_0_CLK_FREQ 1843200
#define UART_NS16550_PORT_1_BASE_ADDR 0x02F8
#define UART_NS16550_PORT_1_IRQ 3
#define UART_NS16550_PORT_1_CLK_FREQ 1843200
#ifdef CONFIG_IOAPIC
#include <drivers/ioapic.h>
#define UART_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
#endif /* CONFIG_IOAPIC */
#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */ #define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
/* PCI definitions */ /* PCI definitions */
#define PCI_BUS_NUMBERS 1 #define PCI_BUS_NUMBERS 1

6
arch/x86/soc/intel_quark/quark_x1000/Kconfig.defconfig.series
View file

@ -184,9 +184,6 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_IRQ_PRI
default 0
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
@ -200,9 +197,6 @@ config UART_NS16550_PORT_1
if UART_NS16550_PORT_1 if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_IRQ_PRI
default 3
config UART_NS16550_PORT_1_OPTIONS config UART_NS16550_PORT_1_OPTIONS
default 0 default 0

20
arch/x86/soc/intel_quark/quark_x1000/dts.fixup
View file

@ -1,10 +1,18 @@
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_F0009000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_9000F000_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_9000F000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_9000F000_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_9000F000_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_9000F000_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_9000F000_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_9000F000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_F0009000_LABEL #define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_9000B000_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_9000B000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_F0008000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME NS16550_9000B000_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_9000B000_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_F0008000_LABEL #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_9000B000_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS NS16550_9000B000_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_9000B000_CLOCK_FREQUENCY
#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS

8
arch/x86/soc/intel_quark/quark_x1000/soc.h
View file

@ -105,10 +105,6 @@
/* /*
* UART * UART
*/ */
#define UART_NS16550_PORT_0_BASE_ADDR 0x9000f000
#define UART_NS16550_PORT_0_IRQ 0
#define UART_NS16550_PORT_0_CLK_FREQ 44236800
#define UART_NS16550_PORT_0_PCI_CLASS 0x07 #define UART_NS16550_PORT_0_PCI_CLASS 0x07
#define UART_NS16550_PORT_0_PCI_BUS 0 #define UART_NS16550_PORT_0_PCI_BUS 0
#define UART_NS16550_PORT_0_PCI_DEV 20 #define UART_NS16550_PORT_0_PCI_DEV 20
@ -117,10 +113,6 @@
#define UART_NS16550_PORT_0_PCI_FUNC 1 #define UART_NS16550_PORT_0_PCI_FUNC 1
#define UART_NS16550_PORT_0_PCI_BAR 0 #define UART_NS16550_PORT_0_PCI_BAR 0
#define UART_NS16550_PORT_1_BASE_ADDR 0x9000b000
#define UART_NS16550_PORT_1_IRQ 17
#define UART_NS16550_PORT_1_CLK_FREQ 44236800
#define UART_NS16550_PORT_1_PCI_CLASS 0x07 #define UART_NS16550_PORT_1_PCI_CLASS 0x07
#define UART_NS16550_PORT_1_PCI_BUS 0 #define UART_NS16550_PORT_1_PCI_BUS 0
#define UART_NS16550_PORT_1_PCI_DEV 20 #define UART_NS16550_PORT_1_PCI_DEV 20

5
arch/xtensa/soc/intel_s1000/dts.fixup
View file

@ -1,8 +1,11 @@
/* SoC level DTS fixup file */ /* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL #define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_80800_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_808000_CLOCK_FREQUENCY
#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS #define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS

7
arch/xtensa/soc/intel_s1000/soc.h
View file

@ -60,12 +60,9 @@
#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ) #define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ)
/* UART - UART0 */ /* UART - UART0 */
#define UART_NS16550_PORT_0_BASE_ADDR 0x00080800 #define CONFIG_UART_NS16550_P0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(\
#define UART_NS16550_PORT_0_CLK_FREQ 38400000
#define UART_NS16550_PORT_0_IRQ 0x00030706
#define UART_NS16550_P0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(\
UART_NS16550_PORT_0_IRQ) UART_NS16550_PORT_0_IRQ)
#define UART_IRQ_FLAGS 0 #define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0
/* I2C - I2C0 */ /* I2C - I2C0 */
#define I2C_DW_0_BASE_ADDR 0x00080400 #define I2C_DW_0_BASE_ADDR 0x00080400

5
drivers/serial/Kconfig.ns16550
View file

@ -63,6 +63,7 @@ menuconfig UART_NS16550_PORT_0
help help
This tells the driver to configure the UART port at boot, depending on This tells the driver to configure the UART port at boot, depending on
the additional configure options below. the additional configure options below.
if !HAS_DTS if !HAS_DTS
config UART_NS16550_PORT_0_NAME config UART_NS16550_PORT_0_NAME
string "Port 0 Device Name" string "Port 0 Device Name"
@ -71,7 +72,6 @@ config UART_NS16550_PORT_0_NAME
help help
This is the device name for UART, and is included in the device This is the device name for UART, and is included in the device
struct. struct.
endif
if !HAS_DTS && !ARC if !HAS_DTS && !ARC
config UART_NS16550_PORT_0_IRQ_PRI config UART_NS16550_PORT_0_IRQ_PRI
@ -82,7 +82,6 @@ config UART_NS16550_PORT_0_IRQ_PRI
The interrupt priority for UART port. The interrupt priority for UART port.
endif endif
if !HAS_DTS
config UART_NS16550_PORT_0_BAUD_RATE config UART_NS16550_PORT_0_BAUD_RATE
int "Port 0 Baud Rate" int "Port 0 Baud Rate"
default 0 default 0
@ -132,7 +131,6 @@ config UART_NS16550_PORT_1_NAME
help help
This is the device name for UART, and is included in the device This is the device name for UART, and is included in the device
struct. struct.
endif
if !HAS_DTS && !ARC if !HAS_DTS && !ARC
config UART_NS16550_PORT_1_IRQ_PRI config UART_NS16550_PORT_1_IRQ_PRI
@ -143,7 +141,6 @@ config UART_NS16550_PORT_1_IRQ_PRI
The interrupt priority for UART port. The interrupt priority for UART port.
endif endif
if !HAS_DTS
config UART_NS16550_PORT_1_BAUD_RATE config UART_NS16550_PORT_1_BAUD_RATE
int "Port 1 Baud Rate" int "Port 1 Baud Rate"
default 0 default 0

21
drivers/serial/uart_ns16550.c
View file

@ -20,6 +20,7 @@
* UART_REG_ADDR_INTERVAL * UART_REG_ADDR_INTERVAL
*/ */
#include <soc.h>
#include <errno.h> #include <errno.h>
#include <kernel.h> #include <kernel.h>
@ -749,7 +750,7 @@ static void irq_config_func_0(struct device *port);
#endif #endif
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_0 = { static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_0 = {
.sys_clk_freq = UART_NS16550_PORT_0_CLK_FREQ, .sys_clk_freq = CONFIG_UART_NS16550_PORT_0_CLK_FREQ,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN #ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = irq_config_func_0, .irq_config_func = irq_config_func_0,
@ -767,7 +768,7 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_0 = {
.pci_dev.bar = UART_NS16550_PORT_0_PCI_BAR, .pci_dev.bar = UART_NS16550_PORT_0_PCI_BAR,
#endif /* CONFIG_UART_NS16550_PORT_0_PCI */ #endif /* CONFIG_UART_NS16550_PORT_0_PCI */
.port = UART_NS16550_PORT_0_BASE_ADDR, .port = CONFIG_UART_NS16550_PORT_0_BASE_ADDR,
.baud_rate = CONFIG_UART_NS16550_PORT_0_BAUD_RATE, .baud_rate = CONFIG_UART_NS16550_PORT_0_BAUD_RATE,
.options = CONFIG_UART_NS16550_PORT_0_OPTIONS, .options = CONFIG_UART_NS16550_PORT_0_OPTIONS,
@ -786,11 +787,11 @@ static void irq_config_func_0(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(UART_NS16550_PORT_0_IRQ, IRQ_CONNECT(CONFIG_UART_NS16550_PORT_0_IRQ,
CONFIG_UART_NS16550_PORT_0_IRQ_PRI, CONFIG_UART_NS16550_PORT_0_IRQ_PRI,
uart_ns16550_isr, DEVICE_GET(uart_ns16550_0), uart_ns16550_isr, DEVICE_GET(uart_ns16550_0),
UART_IRQ_FLAGS); CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS);
irq_enable(UART_NS16550_PORT_0_IRQ); irq_enable(CONFIG_UART_NS16550_PORT_0_IRQ);
} }
#endif #endif
@ -803,7 +804,7 @@ static void irq_config_func_1(struct device *port);
#endif #endif
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_1 = { static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_1 = {
.sys_clk_freq = UART_NS16550_PORT_1_CLK_FREQ, .sys_clk_freq = CONFIG_UART_NS16550_PORT_1_CLK_FREQ,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN #ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_config_func = irq_config_func_1, .irq_config_func = irq_config_func_1,
@ -821,7 +822,7 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_1 = {
.pci_dev.bar = UART_NS16550_PORT_1_PCI_BAR, .pci_dev.bar = UART_NS16550_PORT_1_PCI_BAR,
#endif /* CONFIG_UART_NS16550_PORT_1_PCI */ #endif /* CONFIG_UART_NS16550_PORT_1_PCI */
.port = UART_NS16550_PORT_1_BASE_ADDR, .port = CONFIG_UART_NS16550_PORT_1_BASE_ADDR,
.baud_rate = CONFIG_UART_NS16550_PORT_1_BAUD_RATE, .baud_rate = CONFIG_UART_NS16550_PORT_1_BAUD_RATE,
.options = CONFIG_UART_NS16550_PORT_1_OPTIONS, .options = CONFIG_UART_NS16550_PORT_1_OPTIONS,
@ -840,11 +841,11 @@ static void irq_config_func_1(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(UART_NS16550_PORT_1_IRQ, IRQ_CONNECT(CONFIG_UART_NS16550_PORT_1_IRQ,
CONFIG_UART_NS16550_PORT_1_IRQ_PRI, CONFIG_UART_NS16550_PORT_1_IRQ_PRI,
uart_ns16550_isr, DEVICE_GET(uart_ns16550_1), uart_ns16550_isr, DEVICE_GET(uart_ns16550_1),
UART_IRQ_FLAGS); CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS);
irq_enable(UART_NS16550_PORT_1_IRQ); irq_enable(CONFIG_UART_NS16550_PORT_1_IRQ);
} }
#endif #endif

2
dts/x86/atom.dtsi
View file

@ -50,6 +50,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x000003f8 0x100>; reg = <0x000003f8 0x100>;
label = "UART_0"; label = "UART_0";
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_EDGE_RISING 3>; interrupts = <4 IRQ_TYPE_EDGE_RISING 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -60,6 +61,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x000002f8 0x100>; reg = <0x000002f8 0x100>;
label = "UART_1"; label = "UART_1";
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_EDGE_RISING 3>; interrupts = <3 IRQ_TYPE_EDGE_RISING 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;

2
dts/x86/ia32.dtsi
View file

@ -52,6 +52,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x000003f8 0x100>; reg = <0x000003f8 0x100>;
label = "UART_0"; label = "UART_0";
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_EDGE_RISING 3>; interrupts = <4 IRQ_TYPE_EDGE_RISING 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -62,6 +63,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x000002f8 0x100>; reg = <0x000002f8 0x100>;
label = "UART_1"; label = "UART_1";
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_EDGE_RISING 3>; interrupts = <3 IRQ_TYPE_EDGE_RISING 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;

2
dts/x86/quark_x1000.dtsi
View file

@ -51,6 +51,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x9000f000 0x400>; reg = <0x9000f000 0x400>;
label = "UART_0"; label = "UART_0";
clock-frequency = <44236800>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW 0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW 0>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
@ -61,6 +62,7 @@
compatible = "ns16550"; compatible = "ns16550";
reg = <0x9000b000 0x400>; reg = <0x9000b000 0x400>;
label = "UART_1"; label = "UART_1";
clock-frequency = <44236800>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW 3>; interrupts = <17 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;