From 4dded19ad7be56895abe22302e07b283cc68a645 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Fri, 4 Apr 2025 14:58:21 +0200 Subject: [PATCH] soc: nordic: Disable cache for soft peripheral RAM region in nRF54H/nRF92 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an entry for the RAM region assigned to soft peripherals that will disable caching for that region. Without this, communication with the FLPR coprocessor cannot be performed correctly. Signed-off-by: Andrzej Głąbek --- soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c index b76fac86bcd..a9e8b3de7a9 100644 --- a/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c +++ b/soc/nordic/common/nrf54hx_nrf92x_mpu_regions.c @@ -18,6 +18,9 @@ #define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \ DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can) +#define SOFTPERIPH_BASE DT_REG_ADDR(DT_NODELABEL(softperiph_ram)) +#define SOFTPERIPH_SIZE DT_REG_SIZE(DT_NODELABEL(softperiph_ram)) + static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS, @@ -40,6 +43,10 @@ static struct arm_mpu_region mpu_regions[] = { MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE, REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)), #endif +#if DT_NODE_EXISTS(DT_NODELABEL(softperiph_ram)) + MPU_REGION_ENTRY("SOFTPERIPH_RAM", SOFTPERIPH_BASE, + REGION_RAM_NOCACHE_ATTR(SOFTPERIPH_BASE, SOFTPERIPH_SIZE)), +#endif }; const struct arm_mpu_config mpu_config = {