diff --git a/drivers/i2c/i2c_ite_enhance.c b/drivers/i2c/i2c_ite_enhance.c
index 9565510e96a..81ba7fb0b28 100644
--- a/drivers/i2c/i2c_ite_enhance.c
+++ b/drivers/i2c/i2c_ite_enhance.c
@@ -1222,11 +1222,9 @@ static int i2c_enhance_target_register(const struct device *dev,
 	/* Software reset */
 	IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;
 	IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;
-	/*
-	 * Set time out register.
-	 * I2C D/E/F clock/data low timeout.
-	 */
-	IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;
+	/* Disable the timeout setting when clock/data are in a low state */
+	IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |
+					 IT8XXX2_I2C_SDA_TIMEOUT_EN);
 	/* Bit stretching */
 	IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;
 	/* Peripheral address(8-bit) */
diff --git a/soc/riscv/riscv-ite/common/chip_chipregs.h b/soc/riscv/riscv-ite/common/chip_chipregs.h
index 1fccd45853b..a3659182959 100644
--- a/soc/riscv/riscv-ite/common/chip_chipregs.h
+++ b/soc/riscv/riscv-ite/common/chip_chipregs.h
@@ -1347,6 +1347,9 @@ enum chip_pll_mode {
 /* 0x13: Nack Status */
 #define IT8XXX2_I2C_NST_CNS           BIT(7)
 #define IT8XXX2_I2C_NST_ID_NACK       BIT(3)
+/* 0x18: Timeout and Arbiter Status */
+#define IT8XXX2_I2C_SCL_TIMEOUT_EN    BIT(7)
+#define IT8XXX2_I2C_SDA_TIMEOUT_EN    BIT(6)
 /* 0x19: Error Status */
 #define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ  BIT(0)
 /* 0x1B: Finish Status */