ITE: drivers/i2c/target: Cleanup the clear status flow of I2C target
IT8XXX2_I2C_STR is a register of read-only, non-writable to clear. Here we can set hardware reset bit in the IT8XXX2_I2C_CTR register to clear the status of IT8XXX2_I2C_STR. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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1 changed files with 7 additions and 7 deletions
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@ -966,10 +966,11 @@ static void target_i2c_isr(const struct device *dev)
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/* Any error */
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if (target_status & E_TARGET_ANY_ERROR) {
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/* Hardware reset */
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IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
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goto end;
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}
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/* Interrupt pending */
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} else if (target_status & IT8XXX2_I2C_INT_PEND) {
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if (target_status & IT8XXX2_I2C_INT_PEND) {
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uint8_t interrupt_status = IT8XXX2_I2C_IRQ_ST(base);
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/* Byte counter enable */
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@ -1021,14 +1022,13 @@ static void target_i2c_isr(const struct device *dev)
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if (interrupt_status & IT8XXX2_I2C_P_CLR) {
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/* Transfer done callback function */
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target_cb->stop(data->target_cfg);
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/* Hardware reset */
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IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
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}
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/* Write clear the peripheral status */
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IT8XXX2_I2C_IRQ_ST(base) = interrupt_status;
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}
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/* Write clear the target status */
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IT8XXX2_I2C_STR(base) = target_status;
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end:
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/* Hardware reset */
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IT8XXX2_I2C_CTR(base) |= IT8XXX2_I2C_HALT;
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}
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#endif
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