soc: add OpenHW Group CVA6 SoC

Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

soc/openhwgroup/cva6/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+
+zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/openhwgroup/cva6/Kconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS
+	bool "Include non-standard cache management operations (currently global cache disable)"
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6

soc/openhwgroup/cva6/Kconfig.defconfig

@@ -0,0 +1,45 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default $(dt_node_int_prop_int,/cpus/cpu@0,timebase-frequency)
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+# highest implemented first-level interrupt is machine external, 11
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 12
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
+# 12 first level, 30 second level
+config MAX_IRQ_PER_AGGREGATOR
+	default 42
+
+# one 2nd level aggregator (PLIC) with 30 interrupts
+# offset of 12
+config NUM_IRQS
+	default 42
+
+config MULTI_LEVEL_INTERRUPTS
+	default y
+
+config 2ND_LEVEL_INTERRUPTS
+	default y
+
+# 1 PLIC
+config NUM_2ND_LEVEL_AGGREGATORS
+	default 1
+
+config PLIC
+	default y
+
+config 3RD_LEVEL_INTERRUPTS
+	default n
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6

soc/openhwgroup/cva6/Kconfig.soc

@@ -0,0 +1,14 @@
+#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+#SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_OPENHWGROUP_CVA6
+	bool
+	help
+	  CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  There is a 64-bit version with imafdc extensions and sv39 MMU and
+	  several 32-bit configurations, optionally with up to imafdc and sv32 MMU.
+
+config SOC_FAMILY
+	default "openhwgroup_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6
+
+rsource "*/Kconfig.soc"

soc/openhwgroup/cva6/cv32a6/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources()
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")

soc/openhwgroup/cva6/cv32a6/Kconfig

@@ -0,0 +1,21 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+# RISCV32 OpenHW Group cva6 configuration options
+
+config SOC_CV32A6
+	select RISCV
+	select RISCV_PRIVILEGED
+	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_HAS_PLIC
+	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH
+	select CPU_HAS_FPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select SCHED_IPI_SUPPORTED
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE

soc/openhwgroup/cva6/cv32a6/Kconfig.soc

@@ -0,0 +1,22 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CV32A6
+	bool
+	select SOC_FAMILY_OPENHWGROUP_CVA6
+	help
+	  CVA6 32-bit RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  This configuration works with the upstream project (https://github.com/openhwgroup/cva6).
+
+config SOC_CV32A6
+	bool
+	select SOC_SERIES_CV32A6
+	help
+	  Minimal CVA6 core in 32-bit configuration: ima extensions, no MMU or PMP,
+	  SoC with CLINT, PLIC, UART, SPI, and Ethernet (Xilinx or lowRISC).
+
+config SOC_SERIES
+	default "cv32a6" if SOC_SERIES_CV32A6
+
+config SOC
+	default "cv32a6" if SOC_CV32A6

soc/openhwgroup/cva6/cv64a6/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources()
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")

soc/openhwgroup/cva6/cv64a6/Kconfig

@@ -0,0 +1,35 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+# RISCV64 OpenHW Group cva6 configuration options
+
+# Shared properties
+config SOC_CV64A6
+	bool
+	select RISCV
+	select RISCV_PRIVILEGED
+	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_HAS_PLIC
+	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH
+	select SCHED_IPI_SUPPORTED
+	select 64BIT
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+
+# Variant with FPU
+config SOC_CV64A6_IMAFDC
+	select SOC_CV64A6
+	select CPU_HAS_FPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
+
+# Variant without FPU
+config SOC_CV64A6_IMAC
+	select SOC_CV64A6

soc/openhwgroup/cva6/cv64a6/Kconfig.soc

@@ -0,0 +1,32 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CV64A6
+	bool
+	select SOC_FAMILY_OPENHWGROUP_CVA6
+	help
+	  CVA6 64-bit RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  This configuration works with the upstream project (https://github.com/openhwgroup/cva6)
+	  as well as the forked project with support for the Xilinx AXI Ethernet Subsystem
+	  (https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet).
+
+config SOC_CV64A6_IMAFDC
+	bool
+	select SOC_SERIES_CV64A6
+	help
+	  Standard CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART,
+	  SPI, and Ethernet (Xilinx or lowRISC). Supports imafdc instruction sets.
+
+config SOC_CV64A6_IMAC
+	bool
+	select SOC_SERIES_CV64A6
+	help
+	  Minimal CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART,
+	  SPI, and Ethernet (Xilinx or lowRISC). Supports imac instruction sets.
+
+config SOC_SERIES
+	default "cv64a6" if SOC_SERIES_CV64A6
+
+config SOC
+	default "cv64a6_imac" if SOC_CV64A6_IMAC
+	default "cv64a6_imafdc" if SOC_CV64A6_IMAFDC

soc/openhwgroup/cva6/cva6.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * @file
+ * OpenHwGroup CVA6 declarations
+ */
+
+#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
+#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CVA6 provides two custom CSRs for cache management:
+ * CSR 7C1 controls the data cache, CSR 7C0 controls the instruction cache.
+ * The least significant bit of the CSRs can be written to enable or disable the cache.
+ * Writing a value of 1 means enabling the cache, writing 0 disables it.
+ * After reset, both caches are enabled by default.
+ *
+ */
+
+#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1
+#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0
+
+#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE  0x1
+#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0
+
+#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE  0x1
+#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */

soc/openhwgroup/cva6/soc.yml

@@ -0,0 +1,13 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+family:
+- name: openhwgroup_cva6
+  series:
+  - name: cv64a6
+    socs:
+    - name: cv64a6_imafdc
+    - name: cv64a6_imac
+  - name: cv32a6
+    socs:
+    - name: cv32a6
+vendor: OpenHW Group

soc/openhwgroup/cva6/soc_cache_management.c

@@ -0,0 +1,38 @@
+/*
+ * Non-standard CVA6 cache management operations.
+ *
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <zephyr/arch/cache.h>
+#include <zephyr/arch/riscv/csr.h>
+#include <zephyr/kernel.h>
+
+#include "cva6.h"
+
+void __weak arch_dcache_enable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE);
+}
+
+void __weak arch_dcache_disable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
+}
+
+void __weak arch_icache_enable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
+}
+
+void __weak arch_icache_disable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
+}
+
+/* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */
+/* this prevents a linker error when the function is not defined */
+void __weak arch_cache_init(void)
+{
+}