39babba9a9
Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
21 lines
584 B
Text
21 lines
584 B
Text
# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
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# SPDX-License-Identifier: Apache-2.0
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# RISCV32 OpenHW Group cva6 configuration options
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config SOC_CV32A6
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select RISCV
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select RISCV_PRIVILEGED
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select ATOMIC_OPERATIONS_BUILTIN
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select RISCV_HAS_PLIC
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select USE_SWITCH_SUPPORTED
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select USE_SWITCH
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select CPU_HAS_FPU
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select SCHED_IPI_SUPPORTED
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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