diff --git a/dts/bindings/cpu/openhwgroup,cva6.yaml b/dts/bindings/cpu/openhwgroup,cva6.yaml new file mode 100644 index 00000000000..e81428bfde3 --- /dev/null +++ b/dts/bindings/cpu/openhwgroup,cva6.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2025 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +description: OpenHW Group CVA6 CPU + +compatible: "openhwgroup,cva6" + +include: riscv,cpus.yaml + +properties: + timebase-frequency: + required: true + type: int + description: Clock speed at which the core-local machine timer operates. diff --git a/dts/riscv/openhwgroup/cv32a6.dtsi b/dts/riscv/openhwgroup/cv32a6.dtsi new file mode 100644 index 00000000000..83ac4bd70fb --- /dev/null +++ b/dts/riscv/openhwgroup/cv32a6.dtsi @@ -0,0 +1,40 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +#include +#include "cva6.dtsi" + +/* + * Least common denominator of CVA6 32-bit CPUs: no FPU, no compressed instructions, + * no MMU, no PMP. + * Boards can overwrite the node if additional configurations are available. + */ +/ { + cpus_0: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu_0: cpu@0 { + clock-frequency = ; + timebase-frequency = ; + device_type = "cpu"; + compatible = "openhwgroup,cva6"; + riscv,isa = "rv32ima"; + /* overwrite in board configuration if sv32 MMU is enabled */ + mmu-type = "riscv,none"; + reg = <0>; + + status = "okay"; + + hlic: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + status = "okay"; + }; + }; + }; +}; diff --git a/dts/riscv/openhwgroup/cv64a6.dtsi b/dts/riscv/openhwgroup/cv64a6.dtsi new file mode 100644 index 00000000000..ff51969c151 --- /dev/null +++ b/dts/riscv/openhwgroup/cv64a6.dtsi @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +#include +#include "cva6.dtsi" +/* + * Application-class configuration of CVA6 64-bit CPUs: + * FPU for 32-bit and 64-bit floats, SV39 MMU. + * + */ +/ { + cpus_0: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu_0: cpu@0 { + clock-frequency = ; + timebase-frequency = ; + device_type = "cpu"; + compatible = "openhwgroup,cva6"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + reg = <0>; + + status = "okay"; + + hlic: interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + status = "okay"; + }; + }; + }; +}; diff --git a/dts/riscv/openhwgroup/cva6.dtsi b/dts/riscv/openhwgroup/cva6.dtsi new file mode 100644 index 00000000000..228c26301f1 --- /dev/null +++ b/dts/riscv/openhwgroup/cva6.dtsi @@ -0,0 +1,151 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright 2024 CISPA Helmholtz Center for Information Security + */ + +#include + +/* + * CVA6 SoC without CPU, which comes in 32 and 64 bit variants + */ +/ { + #address-cells = <0x01>; + #size-cells = <0x01>; + + clocks { + + clk_cpu { + #clock-cells = <0x00>; + clock-frequency = ; + compatible = "fixed-clock"; + }; + + clk_bus: clk_bus_0 { + #clock-cells = <0x00>; + clock-frequency = ; + compatible = "fixed-clock"; + }; + }; + + soc { + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + /* Xilinx MIG memory controller */ + memory0: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + status = "okay"; + }; + + /* RISC-V Platform-level interrupt controller */ + plic: interrupt-controller@c000000 { + compatible = "sifive,plic-1.0.0"; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&hlic 11 &hlic 9>; + reg = <0x0c000000 0x4000000>; + riscv,max-priority = <7>; + riscv,ndev = <30>; + status = "okay"; + }; + + /* USB UART */ + uart0: serial@10000000 { + clock-frequency = <50000000>; + clocks = <&clk_bus>; + compatible = "ns16550"; + current-speed = <115200>; + device_type = "serial"; + reg = <0x10000000 0x10000>; + reg-shift = <0x02>; + parity = "none"; + stop-bits = "1"; + data-bits = <8>; + interrupt-parent = <&plic>; + interrupts = <1 0x04>; + status = "disabled"; + }; + + /* SPI controller, connected to SD card */ + spi0: axi_quad_spi@20000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "xlnx,xps-spi-2.00.a"; + reg = <0x20000000 0x10000>; + xlnx,num-ss-bits = <0x01>; + xlnx,num-transfer-bits = <0x8>; + interrupts=<2 0x2>; + interrupt-parent=<&plic>; + clocks=<&clk_bus>; + status = "disabled"; + }; + + /* + * Core-local interrupt controller according to RISC-V spec + */ + clint: clint@2000000 { + compatible = "sifive,clint0"; + reg = <0x2000000 0x40000>; + interrupts-extended = <&hlic 3 &hlic 7>; + status = "disabled"; + }; + + /* + * Xilinx AXI DMA. + * Part of the Xilinx AXI Ethernet Subsystem. + * Only on CISPA board. + */ + dma0: dma@41e00000 { + #dma-cells = <0x01>; + clock-frequency = ; + clock-names = "s_axi_lite_aclk"; + clocks = <&clk_bus>; + compatible = "xlnx,eth-dma"; + reg = <0x41e00000 0x10000>; + xlnx,addrwidth = <0x40>; + xlnx,include-dre; + xlnx,num-queues = <0x1>; + interrupt-parent = <&plic>; + // TX - RX + // active-high level-triggered + interrupts = <8 4>, <9 4>; + // TX and RX + dma-channels = <2>; + status = "disabled"; + }; + + /* + * LowRISC ethernet subsystem. + * Only on OpenHW Group board. + */ + eth: lowrisc-eth@30000000 { + compatible = "lowrisc-eth"; + device_type = "network"; + interrupt-parent = <&plic>; + interrupts = <3 0>; + reg = <0x0 0x30000000 0x0 0x8000>; + status = "disabled"; + }; + + /* Xilinx GPIO, connected to LEDs */ + xlnx_gpio: gpio@40000000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x40000000 0x0 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x8>; + xlnx,gpio2-width = <0x8>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + status = "disabled"; + }; + }; +}; diff --git a/soc/openhwgroup/cva6/CMakeLists.txt b/soc/openhwgroup/cva6/CMakeLists.txt new file mode 100644 index 00000000000..f27fe1213a2 --- /dev/null +++ b/soc/openhwgroup/cva6/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/openhwgroup/cva6/Kconfig b/soc/openhwgroup/cva6/Kconfig new file mode 100644 index 00000000000..820e68f170d --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_OPENHWGROUP_CVA6 + +config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS + bool "Include non-standard cache management operations (currently global cache disable)" + +rsource "*/Kconfig" + +endif # SOC_FAMILY_OPENHWGROUP_CVA6 diff --git a/soc/openhwgroup/cva6/Kconfig.defconfig b/soc/openhwgroup/cva6/Kconfig.defconfig new file mode 100644 index 00000000000..4b4962dc332 --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_OPENHWGROUP_CVA6 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default $(dt_node_int_prop_int,/cpus/cpu@0,timebase-frequency) + +config RISCV_SOC_INTERRUPT_INIT + default y + +# highest implemented first-level interrupt is machine external, 11 +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +# 12 first level, 30 second level +config MAX_IRQ_PER_AGGREGATOR + default 42 + +# one 2nd level aggregator (PLIC) with 30 interrupts +# offset of 12 +config NUM_IRQS + default 42 + +config MULTI_LEVEL_INTERRUPTS + default y + +config 2ND_LEVEL_INTERRUPTS + default y + +# 1 PLIC +config NUM_2ND_LEVEL_AGGREGATORS + default 1 + +config PLIC + default y + +config 3RD_LEVEL_INTERRUPTS + default n + +endif # SOC_FAMILY_OPENHWGROUP_CVA6 diff --git a/soc/openhwgroup/cva6/Kconfig.soc b/soc/openhwgroup/cva6/Kconfig.soc new file mode 100644 index 00000000000..36b8f2e29a2 --- /dev/null +++ b/soc/openhwgroup/cva6/Kconfig.soc @@ -0,0 +1,14 @@ +#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +#SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_OPENHWGROUP_CVA6 + bool + help + CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs. + There is a 64-bit version with imafdc extensions and sv39 MMU and + several 32-bit configurations, optionally with up to imafdc and sv32 MMU. + +config SOC_FAMILY + default "openhwgroup_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6 + +rsource "*/Kconfig.soc" diff --git a/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt new file mode 100644 index 00000000000..da374abd68f --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() + +zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".") diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig b/soc/openhwgroup/cva6/cv32a6/Kconfig new file mode 100644 index 00000000000..b5dbe0ba387 --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/Kconfig @@ -0,0 +1,21 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +# RISCV32 OpenHW Group cva6 configuration options + +config SOC_CV32A6 + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_HAS_PLIC + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select SCHED_IPI_SUPPORTED + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig.soc b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc new file mode 100644 index 00000000000..a1c8eac6e19 --- /dev/null +++ b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc @@ -0,0 +1,22 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV32A6 + bool + select SOC_FAMILY_OPENHWGROUP_CVA6 + help + CVA6 32-bit RISC-V CPUs, commonly used as soft cores on FPGAs. + This configuration works with the upstream project (https://github.com/openhwgroup/cva6). + +config SOC_CV32A6 + bool + select SOC_SERIES_CV32A6 + help + Minimal CVA6 core in 32-bit configuration: ima extensions, no MMU or PMP, + SoC with CLINT, PLIC, UART, SPI, and Ethernet (Xilinx or lowRISC). + +config SOC_SERIES + default "cv32a6" if SOC_SERIES_CV32A6 + +config SOC + default "cv32a6" if SOC_CV32A6 diff --git a/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt new file mode 100644 index 00000000000..da374abd68f --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources() + +zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".") diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig b/soc/openhwgroup/cva6/cv64a6/Kconfig new file mode 100644 index 00000000000..64d7f54bd04 --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/Kconfig @@ -0,0 +1,35 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +# RISCV64 OpenHW Group cva6 configuration options + +# Shared properties +config SOC_CV64A6 + bool + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_HAS_PLIC + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select SCHED_IPI_SUPPORTED + select 64BIT + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + +# Variant with FPU +config SOC_CV64A6_IMAFDC + select SOC_CV64A6 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select RISCV_ISA_EXT_F + select RISCV_ISA_EXT_D + +# Variant without FPU +config SOC_CV64A6_IMAC + select SOC_CV64A6 diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig.soc b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc new file mode 100644 index 00000000000..c3be28de834 --- /dev/null +++ b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV64A6 + bool + select SOC_FAMILY_OPENHWGROUP_CVA6 + help + CVA6 64-bit RISC-V CPUs, commonly used as soft cores on FPGAs. + This configuration works with the upstream project (https://github.com/openhwgroup/cva6) + as well as the forked project with support for the Xilinx AXI Ethernet Subsystem + (https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet). + +config SOC_CV64A6_IMAFDC + bool + select SOC_SERIES_CV64A6 + help + Standard CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART, + SPI, and Ethernet (Xilinx or lowRISC). Supports imafdc instruction sets. + +config SOC_CV64A6_IMAC + bool + select SOC_SERIES_CV64A6 + help + Minimal CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART, + SPI, and Ethernet (Xilinx or lowRISC). Supports imac instruction sets. + +config SOC_SERIES + default "cv64a6" if SOC_SERIES_CV64A6 + +config SOC + default "cv64a6_imac" if SOC_CV64A6_IMAC + default "cv64a6_imafdc" if SOC_CV64A6_IMAFDC diff --git a/soc/openhwgroup/cva6/cva6.h b/soc/openhwgroup/cva6/cva6.h new file mode 100644 index 00000000000..f2bd8a3432e --- /dev/null +++ b/soc/openhwgroup/cva6/cva6.h @@ -0,0 +1,40 @@ +/* + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * @file + * OpenHwGroup CVA6 declarations + */ + +#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H +#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CVA6 provides two custom CSRs for cache management: + * CSR 7C1 controls the data cache, CSR 7C0 controls the instruction cache. + * The least significant bit of the CSRs can be written to enable or disable the cache. + * Writing a value of 1 means enabling the cache, writing 0 disables it. + * After reset, both caches are enabled by default. + * + */ + +#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1 +#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0 + +#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE 0x1 +#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0 + +#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE 0x1 +#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0 + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */ diff --git a/soc/openhwgroup/cva6/soc.yml b/soc/openhwgroup/cva6/soc.yml new file mode 100644 index 00000000000..bd250f81d4b --- /dev/null +++ b/soc/openhwgroup/cva6/soc.yml @@ -0,0 +1,13 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +family: +- name: openhwgroup_cva6 + series: + - name: cv64a6 + socs: + - name: cv64a6_imafdc + - name: cv64a6_imac + - name: cv32a6 + socs: + - name: cv32a6 +vendor: OpenHW Group diff --git a/soc/openhwgroup/cva6/soc_cache_management.c b/soc/openhwgroup/cva6/soc_cache_management.c new file mode 100644 index 00000000000..baa34cb9e59 --- /dev/null +++ b/soc/openhwgroup/cva6/soc_cache_management.c @@ -0,0 +1,38 @@ +/* + * Non-standard CVA6 cache management operations. + * + * Copyright(c) 2024, CISPA Helmholtz Center for Information Security + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +#include "cva6.h" + +void __weak arch_dcache_enable(void) +{ + csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE); +} + +void __weak arch_dcache_disable(void) +{ + csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE); +} + +void __weak arch_icache_enable(void) +{ + csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE); +} + +void __weak arch_icache_disable(void) +{ + csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE); +} + +/* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */ +/* this prevents a linker error when the function is not defined */ +void __weak arch_cache_init(void) +{ +}