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soc: adi: max32: Enable primary core to configure/start secondary core

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Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
This commit is contained in:
Maureen Helm 2024-06-12 14:20:33 -05:00 • committed by Benjamin Cabé
commit 398d9e3d49
2 changed files with 39 additions and 0 deletions
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29
soc/adi/max32/Kconfig
View file

@ -16,6 +16,21 @@ config SOC_FAMILY_MAX32_M4
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
config SOC_MAX32655_M4
select MAX32_HAS_SECONDARY_RV32
config SOC_MAX32680_M4
select MAX32_HAS_SECONDARY_RV32
config SOC_MAX32690_M4
select MAX32_HAS_SECONDARY_RV32
config SOC_MAX78000_M4
select MAX32_HAS_SECONDARY_RV32
config SOC_MAX78002_M4
select MAX32_HAS_SECONDARY_RV32
if SOC_FAMILY_MAX32
config MAX32_ON_ENTER_CPU_IDLE_HOOK
@ -28,4 +43,18 @@ config MAX32_ON_ENTER_CPU_IDLE_HOOK
If needed, this hook can be used to prevent the CPU from actually
entering sleep by skipping the WFE/WFI instruction.
config MAX32_HAS_SECONDARY_RV32
bool
config MAX32_SECONDARY_RV32
bool "Secondary RISC-V core enable"
depends on MAX32_HAS_SECONDARY_RV32
DT_CHOSEN_Z_CODE_RV32_PARTITION := zephyr,code-rv32-partition
config MAX32_SECONDARY_RV32_BOOT_ADDRESS
hex "Secondary RISC-V core boot address"
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_RV32_PARTITION))
depends on MAX32_SECONDARY_RV32
endif # SOC_FAMILY_MAX32

10
soc/adi/max32/soc.c
View file

@ -14,6 +14,10 @@
#include <wrap_max32_sys.h>
#ifdef CONFIG_MAX32_SECONDARY_RV32
#include <fcr_regs.h>
#endif
#if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
bool z_arm_on_enter_cpu_idle(void)
{
@ -31,4 +35,10 @@ void soc_early_init_hook(void)
{
/* Apply device related preinit configuration */
max32xx_system_init();
#ifdef CONFIG_MAX32_SECONDARY_RV32
MXC_FCR->urvbootaddr = CONFIG_MAX32_SECONDARY_RV32_BOOT_ADDRESS;
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CPU1);
MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1;
#endif /* CONFIG_MAX32_SECONDARY_RV32 */
}