diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig
index 87b94d0801d..2bddfc6e556 100644
--- a/soc/adi/max32/Kconfig
+++ b/soc/adi/max32/Kconfig
@@ -16,6 +16,21 @@ config SOC_FAMILY_MAX32_M4
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 
+config SOC_MAX32655_M4
+	select MAX32_HAS_SECONDARY_RV32
+
+config SOC_MAX32680_M4
+	select MAX32_HAS_SECONDARY_RV32
+
+config SOC_MAX32690_M4
+	select MAX32_HAS_SECONDARY_RV32
+
+config SOC_MAX78000_M4
+	select MAX32_HAS_SECONDARY_RV32
+
+config SOC_MAX78002_M4
+	select MAX32_HAS_SECONDARY_RV32
+
 if SOC_FAMILY_MAX32
 
 config MAX32_ON_ENTER_CPU_IDLE_HOOK
@@ -28,4 +43,18 @@ config MAX32_ON_ENTER_CPU_IDLE_HOOK
 	  If needed, this hook can be used to prevent the CPU from actually
 	  entering sleep by skipping the WFE/WFI instruction.
 
+config MAX32_HAS_SECONDARY_RV32
+	bool
+
+config MAX32_SECONDARY_RV32
+	bool "Secondary RISC-V core enable"
+	depends on MAX32_HAS_SECONDARY_RV32
+
+DT_CHOSEN_Z_CODE_RV32_PARTITION := zephyr,code-rv32-partition
+
+config MAX32_SECONDARY_RV32_BOOT_ADDRESS
+	hex "Secondary RISC-V core boot address"
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_RV32_PARTITION))
+	depends on MAX32_SECONDARY_RV32
+
 endif # SOC_FAMILY_MAX32
diff --git a/soc/adi/max32/soc.c b/soc/adi/max32/soc.c
index c509e8e5cf3..fc24e6e1d82 100644
--- a/soc/adi/max32/soc.c
+++ b/soc/adi/max32/soc.c
@@ -14,6 +14,10 @@
 
 #include <wrap_max32_sys.h>
 
+#ifdef CONFIG_MAX32_SECONDARY_RV32
+#include <fcr_regs.h>
+#endif
+
 #if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
 bool z_arm_on_enter_cpu_idle(void)
 {
@@ -31,4 +35,10 @@ void soc_early_init_hook(void)
 {
 	/* Apply device related preinit configuration */
 	max32xx_system_init();
+
+#ifdef CONFIG_MAX32_SECONDARY_RV32
+	MXC_FCR->urvbootaddr = CONFIG_MAX32_SECONDARY_RV32_BOOT_ADDRESS;
+	MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CPU1);
+	MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1;
+#endif /* CONFIG_MAX32_SECONDARY_RV32 */
 }