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drivers: dma: siwx91x: Do not cache shared memory

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Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
Jérôme Pouiller 2025-03-12 15:51:30 +01:00 • committed by Benjamin Cabé
commit 382a6d5d32
1 changed files with 2 additions and 2 deletions
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4
dts/arm/silabs/siwg917.dtsi
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@ -36,14 +36,14 @@
compatible = "zephyr,memory-region", "mmio-sram"; compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x0002fc00 DT_SIZE_K(1)>; reg = <0x0002fc00 DT_SIZE_K(1)>;
zephyr,memory-region = "dma0"; zephyr,memory-region = "dma0";
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>; zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
}; };
sram_dma1: memory-dma@24061c00 { sram_dma1: memory-dma@24061c00 {
compatible = "zephyr,memory-region", "mmio-sram"; compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x24061c00 DT_SIZE_K(1)>; reg = <0x24061c00 DT_SIZE_K(1)>;
zephyr,memory-region = "dma1"; zephyr,memory-region = "dma1";
zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>; zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
}; };
bt_hci0: bt_hci { bt_hci0: bt_hci {