From 382a6d5d321f996099aa3da928d2d548ac8fa594 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Pouiller?= <jerome.pouiller@silabs.com>
Date: Wed, 12 Mar 2025 15:51:30 +0100
Subject: [PATCH] drivers: dma: siwx91x: Do not cache shared memory
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Memory areas for DMA descriptors are shared with the DMA hardware block.
There area should be cached by the CPU.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
---
 dts/arm/silabs/siwg917.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi
index 94f7f6b1093..de037707c3c 100644
--- a/dts/arm/silabs/siwg917.dtsi
+++ b/dts/arm/silabs/siwg917.dtsi
@@ -36,14 +36,14 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x0002fc00 DT_SIZE_K(1)>;
 		zephyr,memory-region = "dma0";
-		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
+		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
 	};
 
 	sram_dma1: memory-dma@24061c00 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x24061c00 DT_SIZE_K(1)>;
 		zephyr,memory-region = "dma1";
-		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM)>;
+		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
 	};
 
 	bt_hci0: bt_hci {