From 3751c396cd02703589d244c05e730f3b264a7da9 Mon Sep 17 00:00:00 2001
From: Daniel Leung <daniel.leung@intel.com>
Date: Thu, 21 Feb 2019 15:05:29 -0800
Subject: [PATCH] soc: intel_s1000: use CAVS DSP wall clock timer for SMP

The DSP wall clock timer is a timer driven directly by
external oscillator and is external to the CPU core(s).
It provides a common and synchronized counter for all
CPU cores (which is useful for SMP), instead of
indepedently running local core timer (xtensa_timer).

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
---
 .../intel_s1000_crb/intel_s1000_crb_defconfig |  1 -
 soc/xtensa/intel_s1000/Kconfig.defconfig      |  4 ++
 soc/xtensa/intel_s1000/soc.h                  | 42 +++++++++++++++----
 3 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig b/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
index 2af6ad963b2..9cbe8b23fde 100644
--- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
+++ b/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
 
 CONFIG_SOC_INTEL_S1000=y
 CONFIG_BOARD_INTEL_S1000_CRB=y
diff --git a/soc/xtensa/intel_s1000/Kconfig.defconfig b/soc/xtensa/intel_s1000/Kconfig.defconfig
index 1003b68ebfc..90304fd3f3e 100644
--- a/soc/xtensa/intel_s1000/Kconfig.defconfig
+++ b/soc/xtensa/intel_s1000/Kconfig.defconfig
@@ -19,4 +19,8 @@ config XTENSA_KERNEL_CPU_PTR_SR
 config SPI_DW_FIFO_DEPTH
 	default 32
 
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 400000000 if XTENSA_TIMER
+	default 38400000 if CAVS_TIMER
+
 endif
diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h
index eef123a8210..820b1c41888 100644
--- a/soc/xtensa/intel_s1000/soc.h
+++ b/soc/xtensa/intel_s1000/soc.h
@@ -39,6 +39,8 @@
 #define CAVS_L2_AGG_INT_LEVEL4			DT_CAVS_ICTL_2_IRQ
 #define CAVS_L2_AGG_INT_LEVEL5			DT_CAVS_ICTL_3_IRQ
 
+#define CAVS_ICTL_INT_CPU_OFFSET(x)		(0x40 * x)
+
 #define IOAPIC_EDGE				0
 #define IOAPIC_HIGH				0
 
@@ -100,6 +102,13 @@ struct soc_mclk_control_regs {
 #define SOC_NUM_LPGPDMAC			3
 #define SOC_NUM_CHANNELS_IN_DMAC		8
 
+/* DSP Wall Clock Timers (0 and 1) */
+#define DSP_WCT_IRQ(x)	\
+	SOC_AGGREGATE_IRQ(0, (23 + x), CAVS_L2_AGG_INT_LEVEL2)
+
+#define DSP_WCT_CS_TA(x)			BIT(x)
+#define DSP_WCT_CS_TT(x)			BIT(4 + x)
+
 /* SOC Resource Allocation Registers */
 #define SOC_RESOURCE_ALLOC_REG_BASE		0x00071A60
 /* bit field definition for LP GPDMA ownership register */
@@ -147,20 +156,39 @@ struct soc_dmic_shim_regs {
 
 struct soc_dsp_shim_regs {
 	u32_t	reserved[8];
-	u64_t	walclk;
-	u64_t	dspwctcs;
-	u64_t	dspwct0c;
-	u64_t	dspwct1c;
-	u32_t	reserved1[14];
+	union {
+		struct {
+			u32_t walclk32_lo;
+			u32_t walclk32_hi;
+		};
+		u64_t	walclk;
+	};
+	u32_t	dspwctcs;
+	u32_t	reserved1[1];
+	union {
+		struct {
+			u32_t dspwct0c32_lo;
+			u32_t dspwct0c32_hi;
+		};
+		u64_t	dspwct0c;
+	};
+	union {
+		struct {
+			u32_t dspwct1c32_lo;
+			u32_t dspwct1c32_hi;
+		};
+		u64_t	dspwct1c;
+	};
+	u32_t	reserved2[14];
 	u32_t	clkctl;
 	u32_t	clksts;
-	u32_t	reserved2[4];
+	u32_t	reserved3[4];
 	u16_t	pwrctl;
 	u16_t	pwrsts;
 	u32_t	lpsctl;
 	u32_t	lpsdmas0;
 	u32_t	lpsdmas1;
-	u32_t	reserved3[22];
+	u32_t	reserved4[22];
 };
 
 /* Global Control registers */