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irq: rv32m1: Fixup IRQ values for multi-level IRQ handling

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Remove the handcoded multi-level IRQ values in device tree.  We now are
able to generate the encoded multi-level IRQ value.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-08-08 14:38:34 -05:00 • committed by Kumar Gala
commit 2c1e0439c7
3 changed files with 24 additions and 45 deletions
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24
dts/riscv/rv32m1_ri5cy.dtsi
View file

@ -93,17 +93,17 @@
&lptmr0 { &lptmr0 {
interrupt-parent = <&intmux0_ch0>; interrupt-parent = <&intmux0_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 7)>; interrupts = <7>;
}; };
&lptmr1 { &lptmr1 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 8)>; interrupts = <8>;
}; };
&lptmr2 { &lptmr2 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 22)>; interrupts = <22>;
}; };
&gpioa { &gpioa {
@ -113,22 +113,22 @@
&gpiob { &gpiob {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 15)>; interrupts = <15>;
}; };
&gpioc { &gpioc {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 16)>; interrupts = <16>;
}; };
&gpiod { &gpiod {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 17)>; interrupts = <17>;
}; };
&gpioe { &gpioe {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 27)>; interrupts = <27>;
}; };
&uart0 { &uart0 {
@ -138,17 +138,17 @@
&uart1 { &uart1 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 13)>; interrupts = <13>;
}; };
&uart2 { &uart2 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 14)>; interrupts = <14>;
}; };
&uart3 { &uart3 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 26)>; interrupts = <26>;
}; };
&i2c0 { &i2c0 {
@ -163,10 +163,10 @@
&i2c2 { &i2c2 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 11)>; interrupts = <11>;
}; };
&i2c3 { &i2c3 {
interrupt-parent = <&intmux0_ch1>; interrupt-parent = <&intmux0_ch1>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 24)>; interrupts = <24>;
}; };

24
dts/riscv/rv32m1_zero_riscy.dtsi
View file

@ -92,12 +92,12 @@
&lptmr0 { &lptmr0 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 6)>; interrupts = <6>;
}; };
&lptmr1 { &lptmr1 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 7)>; interrupts = <7>;
}; };
&lptmr2 { &lptmr2 {
@ -107,22 +107,22 @@
&gpioa { &gpioa {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 25)>; interrupts = <25>;
}; };
&gpiob { &gpiob {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 26)>; interrupts = <26>;
}; };
&gpioc { &gpioc {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 27)>; interrupts = <27>;
}; };
&gpiod { &gpiod {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 28)>; interrupts = <28>;
}; };
&gpioe { &gpioe {
@ -132,17 +132,17 @@
&uart0 { &uart0 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 21)>; interrupts = <21>;
}; };
&uart1 { &uart1 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 22)>; interrupts = <22>;
}; };
&uart2 { &uart2 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 23)>; interrupts = <23>;
}; };
&uart3 { &uart3 {
@ -152,17 +152,17 @@
&i2c0 { &i2c0 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 13)>; interrupts = <13>;
}; };
&i2c1 { &i2c1 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 14)>; interrupts = <14>;
}; };
&i2c2 { &i2c2 {
interrupt-parent = <&intmux1_ch0>; interrupt-parent = <&intmux1_ch0>;
interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 15)>; interrupts = <15>;
}; };
&i2c3 { &i2c3 {

21
include/dt-bindings/interrupt-controller/openisa-intmux.h
View file

@ -7,19 +7,6 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_OPENISA_INTMUX_H_ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_OPENISA_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_OPENISA_INTMUX_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_OPENISA_INTMUX_H_
/*
* Symbols for intmux channels, for DT readability when using
* INTMUX_LEVEL2_IRQ().
*/
#define INTMUX_CH0 0
#define INTMUX_CH1 1
#define INTMUX_CH2 2
#define INTMUX_CH3 3
#define INTMUX_CH4 4
#define INTMUX_CH5 5
#define INTMUX_CH6 6
#define INTMUX_CH7 7
/* /*
* Level 1 IRQ offsets for each INTMUX channel. * Level 1 IRQ offsets for each INTMUX channel.
*/ */
@ -32,12 +19,4 @@
#define INTMUX_CH6_IRQ 30 #define INTMUX_CH6_IRQ 30
#define INTMUX_CH7_IRQ 31 #define INTMUX_CH7_IRQ 31
/*
* Multi-level IRQ number for a INTMUX channel/line interrupt.
*
* See gen_isr_tables.py for details.
*/
#define INTMUX_LEVEL2_IRQ(channel, line) \
((((line) + 1) << 8) | ((channel) + INTMUX_CH0_IRQ))
#endif #endif