From 2aa071c7ada492039b528f08d135528c3939ef01 Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Mon, 4 Nov 2024 15:22:45 +0700 Subject: [PATCH] drivers: pinctrl: Support pinctrl driver for Renesas RX Intial support of pinctrl driver for Renesas RX MCU family. This support base on using Renesas RX driver package in hal_renesas layer Signed-off-by: Duy Nguyen Signed-off-by: Phi Tran --- drivers/pinctrl/renesas/CMakeLists.txt | 1 + drivers/pinctrl/renesas/rx/Kconfig | 11 + .../pinctrl/renesas/rx/pinctrl_renesas_rx.c | 153 +++++++ dts/bindings/pinctrl/renesas,rx-pinctrl.yaml | 105 +++++ dts/bindings/pinctrl/renesas,rx-pinmux.yaml | 25 ++ dts/rx/renesas/rx130-common.dtsi | 1 + .../dt-bindings/pinctrl/renesas/pinctrl-rx.h | 397 ++++++++++++++++++ modules/Kconfig.renesas | 10 + soc/renesas/rx/include/pinctrl_soc.h | 85 ++++ 9 files changed, 788 insertions(+) create mode 100644 drivers/pinctrl/renesas/rx/Kconfig create mode 100644 drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c create mode 100644 dts/bindings/pinctrl/renesas,rx-pinctrl.yaml create mode 100644 dts/bindings/pinctrl/renesas,rx-pinmux.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h create mode 100644 soc/renesas/rx/include/pinctrl_soc.h diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt index 0382b0be253..25bb624acc1 100644 --- a/drivers/pinctrl/renesas/CMakeLists.txt +++ b/drivers/pinctrl/renesas/CMakeLists.txt @@ -3,6 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RX rx/pinctrl_renesas_rx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c) diff --git a/drivers/pinctrl/renesas/rx/Kconfig b/drivers/pinctrl/renesas/rx/Kconfig new file mode 100644 index 00000000000..1bd9c4ff16d --- /dev/null +++ b/drivers/pinctrl/renesas/rx/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_RENESAS_RX + bool "Renesas RX series pin controller driver" + default y + depends on DT_HAS_RENESAS_RX_PINCTRL_ENABLED + select USE_RX_RDP_MPC + select USE_RX_RDP_GPIO + help + Enable Renesas RX series pin controller driver. diff --git a/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c b/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c new file mode 100644 index 00000000000..f6a2fcadec5 --- /dev/null +++ b/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* Renesas FIT module for iodefine.h data structures */ +#include "platform.h" +#include "r_gpio_rx_if.h" +#include "r_mpc_rx_if.h" + +#define PORT_POS (8) + +extern const uint8_t g_gpio_open_drain_n_support[]; +extern const uint8_t g_gpio_pull_up_support[]; +extern const uint8_t g_gpio_dscr_support[]; + +static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number, + uint8_t pin_number) +{ + if ((check_array[port_number] & (1 << pin_number)) != 0) { + return true; + } else { + return false; + } +} + +static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value) +{ + gpio_port_pin_t port_pin; + bool pin_check; + int ret = 0; + + port_pin = (pin->port_num << PORT_POS) | pin->pin_num; + pin_check = gpio_pin_function_check(g_gpio_pull_up_support, pin->port_num, pin->pin_num); + + if (pin_check) { + ret = R_GPIO_PinControl(port_pin, (value ? GPIO_CMD_IN_PULL_UP_ENABLE + : GPIO_CMD_IN_PULL_UP_DISABLE)); + } + + return ret; +} + +static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value) +{ + gpio_port_pin_t port_pin; + bool pin_check; + int ret = 0; + + port_pin = (pin->port_num << PORT_POS) | pin->pin_num; + pin_check = gpio_pin_function_check(g_gpio_dscr_support, pin->port_num, pin->pin_num); + + if (pin_check) { + ret = R_GPIO_PinControl(port_pin, + (value ? GPIO_CMD_DSCR_ENABLE : GPIO_CMD_DSCR_DISABLE)); + } + + return ret; +} + +static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value) +{ + gpio_port_pin_t port_pin; + bool pin_check; + int ret = 0; + + port_pin = (pin->port_num << PORT_POS) | pin->pin_num; + pin_check = + gpio_pin_function_check(g_gpio_open_drain_n_support, pin->port_num, pin->pin_num); + + if (pin_check) { + ret = R_GPIO_PinControl( + port_pin, (value ? GPIO_CMD_OUT_OPEN_DRAIN_N_CHAN : GPIO_CMD_OUT_CMOS)); + } + + return ret; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + gpio_port_pin_t port_pin; + mpc_config_t pconfig = { + .pin_function = 0x0, + .irq_enable = false, + .analog_enable = false, + }; + int ret; + + for (uint8_t i = 0U; i < pin_cnt; i++) { + const pinctrl_soc_pin_t *pin = &pins[i]; + + port_pin = (pin->port_num << PORT_POS) | pin->pin_num; + + /* Set PMR register to 0 before setting pin control register */ + ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_GPIO); + if (ret != 0) { + return -EINVAL; + } + + /* Set output high */ + if (pin->cfg.output_high) { + R_GPIO_PinWrite(port_pin, GPIO_LEVEL_HIGH); + } + + /* Set port direction */ + if (pin->cfg.output_enable) { + R_GPIO_PinDirectionSet(port_pin, GPIO_DIRECTION_OUTPUT); + } + + /* Set pull-up */ + ret = pinctrl_configure_pullup(pin, pin->cfg.bias_pull_up); + + if (ret != 0) { + return -EINVAL; + } + + /* Set open-drain */ + ret = pinctrl_configure_opendrain(pin, pin->cfg.drive_open_drain); + + if (ret != 0) { + return -EINVAL; + } + + /* Set drive-strength */ + ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength); + + if (ret != 0) { + return -EINVAL; + } + + /* Set pin function */ + pconfig.analog_enable = pin->cfg.analog_enable; + pconfig.pin_function = pin->cfg.psels; + ret = R_MPC_Write(port_pin, &pconfig); + if (ret != 0) { + return -EINVAL; + } + + /* Set MODE */ + if (pin->cfg.pin_mode) { + ret = R_GPIO_PinControl(port_pin, GPIO_CMD_ASSIGN_TO_PERIPHERAL); + if (ret != 0) { + return -EINVAL; + } + } + } + + return 0; +} diff --git a/dts/bindings/pinctrl/renesas,rx-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rx-pinctrl.yaml new file mode 100644 index 00000000000..da339cba007 --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rx-pinctrl.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + description: | + The Renesas RX pin controller is a node responsible for controlling + pin function selection and pin properties + + The node has the 'pinctrl' node label set in your SoC's devicetree, + so you can modify it like this: + + &pinctrl { + /* your modifications go here */ + }; + + All device pin configurations should be placed in child nodes of the + 'pinctrl' node, as shown in this example: + + /* You can put this in places like a board-pinctrl.dtsi file in + * your board directory, or a devicetree overlay in your application. + */ + + /* include pre-defined combinations for the SoC variant used by the board */ + #include + + &pinctrl { + sci1_default: sci1_default { + group1 { + psels = ; /* TX */ + drive-strength = "medium"; + }; + group2 { + psels = ; /* RX */ + drive-strength = "medium"; + }; + }; + }; + + The 'sci1_default' child node encodes the pin configurations for a + particular state of a device; in this case, the default (that is, active) + state. + + As shown, pin configurations are organized in groups within each child node. + Each group can specify a list of pin function selections in the 'psels' + property. + + A group can also specify shared pin properties common to all the specified + pins, such as the 'input-enable' property in group 2. Here is a list of + supported standard pin properties: + + - bias-disable: Disable pull-up/down (default, not required). + - bias-pull-up: Enable pull-up resistor. + - input-enable: Enable input from the pin. + - drive-strength: Set the drive strength of the pin. Possible + values are: normal, high. + + To link pin configurations with a device, use a pinctrl-N property for some + number N, like this example you could place in your board's DTS file: + + #include "board-pinctrl.dtsi" + + &sci1 { + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; + }; + +compatible: "renesas,rx-pinctrl" + +include: base.yaml + +child-binding: + description: | + Definitions for a pinctrl state. + child-binding: + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-up + - input-enable + - output-enable + - output-high + - drive-open-drain + + properties: + psels: + required: true + type: array + description: | + An array of pins sharing the same group properties. Each + element of the array is an integer constructed from the + pin number and the alternative function of the pin. + drive-strength: + type: string + enum: + - "normal" + - "high" + default: "normal" + description: | + The drive strength of a pin. The default value is normal, as this + is the power on reset value. + renesas,analog-enable: + type: boolean + description: enable analog input diff --git a/dts/bindings/pinctrl/renesas,rx-pinmux.yaml b/dts/bindings/pinctrl/renesas,rx-pinmux.yaml new file mode 100644 index 00000000000..37932b2338e --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rx-pinmux.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Rensas RX Pinmux (Multi Function Pin Controller, MPC) + +compatible: "renesas,rx-pinmux" + +include: base.yaml + +properties: + reg: + required: true + + "#pinmux-cells": + type: int + required: true + const: 2 + description: number of items in a pinmux specifier + +pinmux-cells: + - pin + - function + +child-binding: + include: pincfg-node.yaml diff --git a/dts/rx/renesas/rx130-common.dtsi b/dts/rx/renesas/rx130-common.dtsi index 1e3c69b4397..9377e159a92 100644 --- a/dts/rx/renesas/rx130-common.dtsi +++ b/dts/rx/renesas/rx130-common.dtsi @@ -10,6 +10,7 @@ #include #include +#include / { #address-cells = <1>; diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h new file mode 100644 index 00000000000..35547c608f6 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_ + +#define RX_PORT_NUM_POS 0 +#define RX_PORT_NUM_MASK 0x1f + +#define RX_PIN_NUM_POS 5 +#define RX_PIN_NUM_MASK 0xf + +#define RX_PSEL_MASK 0x1f +#define RX_PSEL_POS 9 + +#define RX_PSEL_SCI_1 0xA +#define RX_PSEL_SCI_6 0xB +#define RX_PSEL_TMR 0x5 +#define RX_PSEL_POE 0x7 + +/* P0nPFS */ +#define RX_PSEL_P0nPFS_HIZ 0x0 +#define RX_PSEL_P0nPFS_ADTRG0 0x1 + +/* P1nPFS */ +#define RX_PSEL_P1nPFS_MTIOC0B 0x01 +#define RX_PSEL_P1nPFS_MTIOC3A 0x01 +#define RX_PSEL_P1nPFS_MTIOC3C 0x01 + +#define RX_PSEL_P1nPFS_MTCLKA 0x02 +#define RX_PSEL_P1nPFS_MTCLKB 0x02 +#define RX_PSEL_P1nPFS_MTIOC3B 0x02 +#define RX_PSEL_P1nPFS_MTIOC3D 0x02 + +#define RX_PSEL_P1nPFS_TMCI1 0x5 +#define RX_PSEL_P1nPFS_TMO1 0x5 +#define RX_PSEL_P1nPFS_TMCI2 0x5 +#define RX_PSEL_P1nPFS_TMO2 0x5 +#define RX_PSEL_P1nPFS_TMRI2 0x5 +#define RX_PSEL_P1nPFS_TMO3 0x5 + +#define RX_PSEL_P1nPFS_RTCOUT 0x7 +#define RX_PSEL_P1nPFS_POE8 0x7 + +#define RX_PSEL_P1nPFS_ADTRG0 0x9 + +#define RX_PSEL_P1nPFS_RXD1 0xA +#define RX_PSEL_P1nPFS_SMISO1 0xA +#define RX_PSEL_P1nPFS_SSCL1 0xA +#define RX_PSEL_P1nPFS_TXD1 0xA +#define RX_PSEL_P1nPFS_SMOSI1 0xA +#define RX_PSEL_P1nPFS_SSDA1 0xA + +#define RX_PSEL_P1nPFS_CTS1 0xB +#define RX_PSEL_P1nPFS_RTS1 0xB +#define RX_PSEL_P1nPFS_SS1 0xB + +#define RX_PSEL_P1nPFS_MOSIA 0xD +#define RX_PSEL_P1nPFS_MISOA 0xD + +#define RX_PSEL_P1nPFS_SCL 0xF +#define RX_PSEL_P1nPFS_SDA 0xF + +#define RX_PSEL_P1nPFS_TS5 0x19 +#define RX_PSEL_P1nPFS_TS6 0x19 + +/* P2nPFS */ +#define RX_PSEL_P2nPFS_MTIOC1A 0x01 +#define RX_PSEL_P2nPFS_MTIOC1B 0x01 +#define RX_PSEL_P2nPFS_MTIOC2A 0x01 +#define RX_PSEL_P2nPFS_MTIOC2B 0x01 +#define RX_PSEL_P2nPFS_MTIOC3B 0x01 +#define RX_PSEL_P2nPFS_MTIOC3D 0x01 +#define RX_PSEL_P2nPFS_MTIOC4A 0x01 +#define RX_PSEL_P2nPFS_MTIOC4C 0x01 + +#define RX_PSEL_P2nPFS_MTCLKA 0x02 +#define RX_PSEL_P2nPFS_MTCLKB 0x02 +#define RX_PSEL_P2nPFS_MTCLKC 0x02 +#define RX_PSEL_P2nPFS_MTCLKD 0x02 + +#define RX_PSEL_P2nPFS_TMCI0 0x5 +#define RX_PSEL_P2nPFS_TMO0 0x5 +#define RX_PSEL_P2nPFS_TMRI0 0x5 +#define RX_PSEL_P2nPFS_TMO1 0x5 +#define RX_PSEL_P2nPFS_TMRI1 0x5 +#define RX_PSEL_P2nPFS_TMCI3 0x5 + +#define RX_PSEL_P2nPFS_ADTRG0 0x9 + +#define RX_PSEL_P2nPFS_RXD0 0xA +#define RX_PSEL_P2nPFS_SMISO0 0xA +#define RX_PSEL_P2nPFS_SSCL0 0xA +#define RX_PSEL_P2nPFS_TXD0 0xA +#define RX_PSEL_P2nPFS_SMOSI0 0xA +#define RX_PSEL_P2nPFS_SSDA0 0xA +#define RX_PSEL_P2nPFS_SCK0 0xA +#define RX_PSEL_P2nPFS_TXD1 0xA +#define RX_PSEL_P2nPFS_SMOSI1 0xA +#define RX_PSEL_P2nPFS_SSDA1 0xA +#define RX_PSEL_P2nPFS_SCK1 0xA + +#define RX_PSEL_P2nPFS_CTS0 0xB +#define RX_PSEL_P2nPFS_RTS0 0xB +#define RX_PSEL_P2nPFS_SS0 0xB + +#define RX_PSEL_P2nPFS_TS3 0x19 +#define RX_PSEL_P2nPFS_TS4 0x19 + +/* P3nPFS */ +#define RX_PSEL_P3nPFS_MTIOC0A 0x01 +#define RX_PSEL_P3nPFS_MTIOC0C 0x01 +#define RX_PSEL_P3nPFS_MTIOC0D 0x01 +#define RX_PSEL_P3nPFS_MTIOC4B 0x01 +#define RX_PSEL_P3nPFS_MTIOC4D 0x01 + +#define RX_PSEL_P3nPFS_TMCI2 0x5 +#define RX_PSEL_P3nPFS_TMO3 0x5 +#define RX_PSEL_P3nPFS_TMRI3 0x5 +#define RX_PSEL_P3nPFS_TMCI3 0x5 + +#define RX_PSEL_P3nPFS_RTCOUT 0x7 +#define RX_PSEL_P3nPFS_POE2 0x7 +#define RX_PSEL_P3nPFS_POE3 0x7 +#define RX_PSEL_P3nPFS_POE8 0x7 + +#define RX_PSEL_P3nPFS_RXD1 0xA +#define RX_PSEL_P3nPFS_SMISO1 0xA +#define RX_PSEL_P3nPFS_SSCL1 0xA + +#define RX_PSEL_P3nPFS_CTS1 0xB +#define RX_PSEL_P3nPFS_RTS1 0xB +#define RX_PSEL_P3nPFS_SS1 0xB +#define RX_PSEL_P3nPFS_RXD6 0xB +#define RX_PSEL_P3nPFS_SMISO6 0xB +#define RX_PSEL_P3nPFS_SSCL6 0xB +#define RX_PSEL_P3nPFS_TXD6 0xB +#define RX_PSEL_P3nPFS_SMOSI6 0xB +#define RX_PSEL_P3nPFS_SSDA6 0xB +#define RX_PSEL_P3nPFS_SCK6 0xB + +#define RX_PSEL_P3nPFS_TS0 0x19 +#define RX_PSEL_P3nPFS_TS1 0x19 +#define RX_PSEL_P3nPFS_TS2 0x19 + +/* P5nPFS */ +#define RX_PSEL_P5nPFS_MTIOC4B 0x01 +#define RX_PSEL_P5nPFS_MTIOC4D 0x01 + +#define RX_PSEL_P5nPFS_TMCI1 0x5 +#define RX_PSEL_P5nPFS_TMO3 0x5 + +#define RX_PSEL_P5nPFS_TS11 0x19 +#define RX_PSEL_P5nPFS_TS12 0x19 + +#define RX_PSEL_P5nPFS_PMC0 0x19 +#define RX_PSEL_P5nPFS_PMC1 0x19 + +/* PAnPFS */ +#define RX_PSEL_PAnPFS_MTIOC4A 0x01 +#define RX_PSEL_PAnPFS_MTIOC0B 0x01 +#define RX_PSEL_PAnPFS_MTIOC0D 0x01 +#define RX_PSEL_PAnPFS_MTIOC5U 0x01 +#define RX_PSEL_PAnPFS_MTIOC5V 0x01 + +#define RX_PSEL_PAnPFS_MTCLKA 0x02 +#define RX_PSEL_PAnPFS_MTCLKB 0x02 +#define RX_PSEL_PAnPFS_MTCLKC 0x02 +#define RX_PSEL_PAnPFS_MTCLKD 0x02 + +#define RX_PSEL_PAnPFS_TMRI0 0x5 +#define RX_PSEL_PAnPFS_TMCI3 0x5 + +#define RX_PSEL_PAnPFS_POE2 0x7 +#define RX_PSEL_PAnPFS_CACREF 0x7 + +#define RX_PSEL_PAnPFS_RXD5 0xA +#define RX_PSEL_PAnPFS_SMISO5 0xA +#define RX_PSEL_PAnPFS_SSCL5 0xA +#define RX_PSEL_PAnPFS_TXD5 0xA +#define RX_PSEL_PAnPFS_SMOSI5 0xA +#define RX_PSEL_PAnPFS_SSDA5 0xA +#define RX_PSEL_PAnPFS_SCK5 0xA + +#define RX_PSEL_PAnPFS_CTS5 0xB +#define RX_PSEL_PAnPFS_RTS5 0xB +#define RX_PSEL_PAnPFS_SS5 0xB + +#define RX_PSEL_PAnPFS_SSLA0 0xD +#define RX_PSEL_PAnPFS_SSLA1 0xD +#define RX_PSEL_PAnPFS_SSLA2 0xD +#define RX_PSEL_PAnPFS_SSLA3 0xD +#define RX_PSEL_PAnPFS_RSPCKA 0xD +#define RX_PSEL_PAnPFS_MOSIA 0xD +#define RX_PSEL_PAnPFS_MISOA 0xD + +#define RX_PSEL_PAnPFS_TS26 0x19 +#define RX_PSEL_PAnPFS_TS27 0x19 +#define RX_PSEL_PAnPFS_TS28 0x19 +#define RX_PSEL_PAnPFS_TS29 0x19 +#define RX_PSEL_PAnPFS_TS30 0x19 +#define RX_PSEL_PAnPFS_TS31 0x19 +#define RX_PSEL_PAnPFS_TS32 0x19 + +/* PBnPFS */ +#define RX_PSEL_PBnPFS_MTIOC0A 0x01 +#define RX_PSEL_PBnPFS_MTIOC0C 0x01 +#define RX_PSEL_PBnPFS_MTIOC2A 0x01 +#define RX_PSEL_PBnPFS_MTIOC3B 0x01 +#define RX_PSEL_PBnPFS_MTIOC3D 0x01 +#define RX_PSEL_PBnPFS_MTIOC5W 0x01 + +#define RX_PSEL_PBnPFS_MTIOC1B 0x02 +#define RX_PSEL_PBnPFS_MTIOC4A 0x02 +#define RX_PSEL_PBnPFS_MTIOC4C 0x02 + +#define RX_PSEL_PBnPFS_TMO0 0x5 +#define RX_PSEL_PBnPFS_TMRI1 0x5 +#define RX_PSEL_PBnPFS_TMCI0 0x5 + +#define RX_PSEL_PBnPFS_POE1 0x7 +#define RX_PSEL_PBnPFS_POE3 0x7 + +#define RX_PSEL_PBnPFS_RXD9 0xA +#define RX_PSEL_PBnPFS_SMISO9 0xA +#define RX_PSEL_PBnPFS_SSCL9 0xA +#define RX_PSEL_PBnPFS_TXD9 0xA +#define RX_PSEL_PBnPFS_SMOSI9 0xA +#define RX_PSEL_PBnPFS_SSDA9 0xA +#define RX_PSEL_PBnPFS_SCK9 0xA + +#define RX_PSEL_PBnPFS_CTS6 0xB +#define RX_PSEL_PBnPFS_RTS6 0xB +#define RX_PSEL_PBnPFS_SS6 0xB +#define RX_PSEL_PBnPFS_CTS9 0xB +#define RX_PSEL_PBnPFS_RTS9 0xB +#define RX_PSEL_PBnPFS_SS9 0xB +#define RX_PSEL_PBnPFS_RXD6 0xB +#define RX_PSEL_PBnPFS_SMISO6 0xB +#define RX_PSEL_PBnPFS_SSCL6 0xB +#define RX_PSEL_PBnPFS_TXD6 0xB +#define RX_PSEL_PBnPFS_SMOSI6 0xB +#define RX_PSEL_PBnPFS_SSDA6 0xB +#define RX_PSEL_PBnPFS_SCK6 0xB + +#define RX_PSEL_PBnPFS_RSPCKA 0xD + +#define RX_PSEL_PBnPFS_CMPOB1 0x10 + +#define RX_PSEL_PBnPFS_TS18 0x19 +#define RX_PSEL_PBnPFS_TS19 0x19 +#define RX_PSEL_PBnPFS_TS20 0x19 +#define RX_PSEL_PBnPFS_TS21 0x19 +#define RX_PSEL_PBnPFS_TS22 0x19 +#define RX_PSEL_PBnPFS_TS23 0x19 +#define RX_PSEL_PBnPFS_TS24 0x19 +#define RX_PSEL_PBnPFS_TS25 0x19 + +/* PCnPFS */ +#define RX_PSEL_PCnPFS_MTIOC3A 0x01 +#define RX_PSEL_PCnPFS_MTIOC3B 0x01 +#define RX_PSEL_PCnPFS_MTIOC3C 0x01 +#define RX_PSEL_PCnPFS_MTIOC3D 0x01 +#define RX_PSEL_PCnPFS_MTIOC4B 0x01 +#define RX_PSEL_PCnPFS_MTIOC4D 0x01 + +#define RX_PSEL_PCnPFS_MTCLKA 0x02 +#define RX_PSEL_PCnPFS_MTCLKB 0x02 +#define RX_PSEL_PCnPFS_MTCLKC 0x02 +#define RX_PSEL_PCnPFS_MTCLKD 0x02 + +#define RX_PSEL_PCnPFS_TMCI1 0x5 +#define RX_PSEL_PCnPFS_TMO2 0x5 +#define RX_PSEL_PCnPFS_TMRI2 0x5 +#define RX_PSEL_PCnPFS_TMCI2 0x5 + +#define RX_PSEL_PCnPFS_POE0 0x7 +#define RX_PSEL_PCnPFS_CACREF 0x7 + +#define RX_PSEL_PCnPFS_RXD5 0xA +#define RX_PSEL_PCnPFS_SMISO5 0xA +#define RX_PSEL_PCnPFS_SSCL5 0xA +#define RX_PSEL_PCnPFS_TXD5 0xA +#define RX_PSEL_PCnPFS_SMOSI5 0xA +#define RX_PSEL_PCnPFS_SSDA5 0xA +#define RX_PSEL_PCnPFS_SCK5 0xA +#define RX_PSEL_PCnPFS_RXD8 0xA +#define RX_PSEL_PCnPFS_SMISO8 0xA +#define RX_PSEL_PCnPFS_SSCL8 0xA +#define RX_PSEL_PCnPFS_TXD8 0xA +#define RX_PSEL_PCnPFS_SMOSI8 0xA +#define RX_PSEL_PCnPFS_SSDA8 0xA +#define RX_PSEL_PCnPFS_SCK8 0xA + +#define RX_PSEL_PCnPFS_CTS5 0xB +#define RX_PSEL_PCnPFS_RTS5 0xB +#define RX_PSEL_PCnPFS_SS5 0xB +#define RX_PSEL_PCnPFS_CTS8 0xB +#define RX_PSEL_PCnPFS_RTS8 0xB +#define RX_PSEL_PCnPFS_SS8 0xB + +#define RX_PSEL_PCnPFS_SSLA0 0xD +#define RX_PSEL_PCnPFS_SSLA1 0xD +#define RX_PSEL_PCnPFS_SSLA2 0xD +#define RX_PSEL_PCnPFS_SSLA3 0xD +#define RX_PSEL_PCnPFS_RSPCKA 0xD +#define RX_PSEL_PCnPFS_MOSIA 0xD +#define RX_PSEL_PCnPFS_MISOA 0xD + +#define RX_PSEL_PCnPFS_TS13 0x19 +#define RX_PSEL_PCnPFS_TS14 0x19 +#define RX_PSEL_PCnPFS_TS15 0x19 +#define RX_PSEL_PCnPFS_TS16 0x19 +#define RX_PSEL_PCnPFS_TS17 0x19 +#define RX_PSEL_PCnPFS_TSCAP 0x19 + +/* PDnPFS */ +#define RX_PSEL_PDnPFS_MTIOC4B 0x01 +#define RX_PSEL_PDnPFS_MTIOC4D 0x01 +#define RX_PSEL_PDnPFS_MTIOC5W 0x01 +#define RX_PSEL_PDnPFS_MTIOC5V 0x01 +#define RX_PSEL_PDnPFS_MTIOC5U 0x01 + +#define RX_PSEL_PDnPFS_POE0 0x7 +#define RX_PSEL_PDnPFS_POE1 0x7 +#define RX_PSEL_PDnPFS_POE2 0x7 +#define RX_PSEL_PDnPFS_POE3 0x7 +#define RX_PSEL_PDnPFS_POE8 0x7 + +#define RX_PSEL_PDnPFS_RXD6 0xB +#define RX_PSEL_PDnPFS_SMISO6 0xB +#define RX_PSEL_PDnPFS_SSCL6 0xB +#define RX_PSEL_PDnPFS_TXD6 0xB +#define RX_PSEL_PDnPFS_SMOSI6 0xB +#define RX_PSEL_PDnPFS_SSDA6 0xB +#define RX_PSEL_PDnPFS_SCK6 0xB + +/* PEnPFS */ +#define RX_PSEL_PEnPFS_MTIOC4A 0x01 +#define RX_PSEL_PEnPFS_MTIOC4B 0x01 +#define RX_PSEL_PEnPFS_MTIOC4C 0x01 +#define RX_PSEL_PEnPFS_MTIOC4D 0x01 + +#define RX_PSEL_PEnPFS_MTIOC1A 0x02 +#define RX_PSEL_PEnPFS_MTIOC2B 0x02 + +#define RX_PSEL_PEnPFS_POE8 0x7 + +#define RX_PSEL_PEnPFS_CLKOUT 0x9 + +#define RX_PSEL_PEnPFS_RXD12 0xC +#define RX_PSEL_PEnPFS_SMISO12 0xC +#define RX_PSEL_PEnPFS_SSCL12 0xC +#define RX_PSEL_PEnPFS_TXD12 0xC +#define RX_PSEL_PEnPFS_SMOSI12 0xC +#define RX_PSEL_PEnPFS_SSDA12 0xC +#define RX_PSEL_PEnPFS_SCK12 0xC +#define RX_PSEL_PEnPFS_TXDX12 0xC +#define RX_PSEL_PEnPFS_RXDX12 0xC +#define RX_PSEL_PEnPFS_SIOX12 0xC +#define RX_PSEL_PEnPFS_CTS12 0xC +#define RX_PSEL_PEnPFS_RTS12 0xC +#define RX_PSEL_PEnPFS_SS12 0xC + +#define RX_PSEL_PEnPFS_CMPOB0 0X10 + +#define RX_PSEL_PEnPFS_TS33 0X19 +#define RX_PSEL_PEnPFS_TS34 0x19 +#define RX_PSEL_PEnPFS_TS35 0x19 + +/* PHnPFS */ +#define RX_PSEL_PHnPFS_TMO0 0x05 +#define RX_PSEL_PHnPFS_TMRI0 0x05 +#define RX_PSEL_PHnPFS_TMCI0 0x05 + +#define RX_PSEL_PHnPFS_CACREF 0x7 + +#define RX_PSEL_PHnPFS_TS7 0x19 +#define RX_PSEL_PHnPFS_TS8 0x19 +#define RX_PSEL_PHnPFS_TS9 0x19 +#define RX_PSEL_PHnPFS_TS10 0x19 + +/* PJnPFS */ +#define RX_PSEL_PJnPFS_MTIOC3A 0x01 +#define RX_PSEL_PJnPFS_MTIOC3C 0x01 + +#define RX_PSEL_PJnPFS_CTS6 0xB +#define RX_PSEL_PJnPFS_TTS6 0xB +#define RX_PSEL_PJnPFS_SS6 0xB + +#define RX_PSEL(psel, port_num, pin_num) \ + (psel << RX_PSEL_POS | pin_num << RX_PIN_NUM_POS | port_num << RX_PORT_NUM_POS) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SOC_RX_COMMON_H_ */ diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 0adb757c814..d37850d438a 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -249,4 +249,14 @@ config HAS_RENESAS_RX_RDP if HAS_RENESAS_RX_RDP +config USE_RX_RDP_MPC + bool + help + Enable RX RDP MPC driver + +config USE_RX_RDP_GPIO + bool + help + Enable RX RDP MPC driver + endif # HAS_RENESAS_RX_RDP diff --git a/soc/renesas/rx/include/pinctrl_soc.h b/soc/renesas/rx/include/pinctrl_soc.h new file mode 100644 index 00000000000..6e0df471d1a --- /dev/null +++ b/soc/renesas/rx/include/pinctrl_soc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_ + +#include +#include +#include + +#include + +#define PORT_POS (8) + +#define PIN_MODE_GPIO (0) +#define PIN_MODE_PERIPHERAL (1) + +struct rx_pin_config { + bool pin_mode; + bool analog_enable; + bool output_enable; + bool output_high; + bool bias_pull_up; + bool drive_open_drain; + uint8_t drive_strength; + uint8_t psels; +}; + +/** + * @brief Type to hold a renesas ra pin's pinctrl configuration. + */ +struct rx_pinctrl_soc_pin { + /** Port number 0..5, A..E, H, J */ + uint32_t port_num: 5; + /** Pin number 0..7 */ + uint32_t pin_num: 4; + /** config pin */ + struct rx_pin_config cfg; +}; + +typedef struct rx_pinctrl_soc_pin pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { \ + .port_num = RX_GET_PORT_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \ + .pin_num = RX_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \ + .cfg = \ + { \ + .pin_mode = PIN_MODE_PERIPHERAL, \ + .analog_enable = DT_PROP(node_id, renesas_analog_enable), \ + .output_enable = DT_PROP(node_id, output_enable), \ + .output_high = DT_PROP(node_id, output_high), \ + .bias_pull_up = DT_PROP(node_id, bias_pull_up), \ + .drive_open_drain = DT_PROP(node_id, drive_open_drain), \ + .drive_strength = DT_ENUM_IDX(node_id, drive_strength), \ + .psels = RX_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)), \ + }, \ + }, + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#define RX_GET_PORT_NUM(pinctrl) (((pinctrl) >> RX_PORT_NUM_POS) & RX_PORT_NUM_MASK) +#define RX_GET_PIN_NUM(pinctrl) (((pinctrl) >> RX_PIN_NUM_POS) & RX_PIN_NUM_MASK) + +#define RX_GET_PSEL(pinctrl) (((pinctrl) >> RX_PSEL_POS) & RX_PSEL_MASK) + +#endif /* ZEPHYR_SOC_RENESAS_RX_COMMON_PINCTRL_SOC_H_ */