dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Kumar Gala
parent
d4a17b4085
commit
20202902f2
304 changed files with 5118 additions and 5118 deletions
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@ -6,27 +6,27 @@
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/* SoC level DTS fixup file */
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#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE
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#define DT_RAM_SIZE CONFIG_SRAM_SIZE
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#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE
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#define DT_ROM_SIZE CONFIG_FLASH_SIZE
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#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
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#define CONFIG_APL_GPIO_BASE_ADDRESS_0 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
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#define CONFIG_APL_GPIO_BASE_ADDRESS_1 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
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#define CONFIG_APL_GPIO_BASE_ADDRESS_2 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
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#define CONFIG_APL_GPIO_BASE_ADDRESS_3 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
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#define CONFIG_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
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#define CONFIG_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
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#define CONFIG_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
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#define CONFIG_APL_GPIO_LABEL DT_INTEL_APL_GPIO_D0C50000_LABEL
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#define CONFIG_APL_GPIO_MEM_SIZE_0 DT_INTEL_APL_GPIO_D0C50000_SIZE_0
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#define CONFIG_APL_GPIO_MEM_SIZE_1 DT_INTEL_APL_GPIO_D0C50000_SIZE_1
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#define CONFIG_APL_GPIO_MEM_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_SIZE_2
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#define CONFIG_APL_GPIO_MEM_SIZE_3 DT_oINTEL_APL_GPIO_D0C50000_SIZE_3
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#define DT_APL_GPIO_BASE_ADDRESS_0 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
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#define DT_APL_GPIO_BASE_ADDRESS_1 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
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#define DT_APL_GPIO_BASE_ADDRESS_2 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
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#define DT_APL_GPIO_BASE_ADDRESS_3 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
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#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0
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#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
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#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
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#define DT_APL_GPIO_LABEL DT_INTEL_APL_GPIO_D0C50000_LABEL
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#define DT_APL_GPIO_MEM_SIZE_0 DT_INTEL_APL_GPIO_D0C50000_SIZE_0
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#define DT_APL_GPIO_MEM_SIZE_1 DT_INTEL_APL_GPIO_D0C50000_SIZE_1
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#define DT_APL_GPIO_MEM_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_SIZE_2
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#define DT_APL_GPIO_MEM_SIZE_3 DT_oINTEL_APL_GPIO_D0C50000_SIZE_3
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/* End of SoC Level DTS fixup file */
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@ -14,11 +14,11 @@
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#include <autoconf.h>
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#include <generated_dts_board.h>
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/* physical address where the kernel is loaded */
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#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR
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#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
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/* physical address of RAM */
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#ifdef CONFIG_XIP
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#define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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#else /* !CONFIG_XIP */
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#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
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#endif /* CONFIG_XIP */
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@ -26,10 +26,10 @@
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
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ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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#else /* !CONFIG_XIP */
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RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
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#endif /* CONFIG_XIP */
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/*
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@ -24,7 +24,7 @@
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MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
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/* ioapic */
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MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
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MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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@ -34,17 +34,17 @@ MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#ifdef CONFIG_UART_NS16550
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#ifdef CONFIG_UART_NS16550_PORT_0
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_1
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_2
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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@ -59,42 +59,42 @@ MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_3_BASE_ADDR, 0x1000,
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#ifdef CONFIG_I2C
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#ifdef CONFIG_I2C_0
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MMU_BOOT_REGION(CONFIG_I2C_0_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_0_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_1
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MMU_BOOT_REGION(CONFIG_I2C_1_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_1_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_2
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MMU_BOOT_REGION(CONFIG_I2C_2_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_2_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_3
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MMU_BOOT_REGION(CONFIG_I2C_3_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_3_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_4
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MMU_BOOT_REGION(CONFIG_I2C_4_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_4_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_5
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MMU_BOOT_REGION(CONFIG_I2C_5_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_5_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_6
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MMU_BOOT_REGION(CONFIG_I2C_6_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_6_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_I2C_7
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MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
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MMU_BOOT_REGION(DT_I2C_7_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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@ -102,17 +102,17 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
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/* for GPIO controller */
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#ifdef CONFIG_GPIO_INTEL_APL
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0,
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CONFIG_APL_GPIO_MEM_SIZE_0,
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MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_0,
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DT_APL_GPIO_MEM_SIZE_0,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1,
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CONFIG_APL_GPIO_MEM_SIZE_1,
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MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_1,
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DT_APL_GPIO_MEM_SIZE_1,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2,
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CONFIG_APL_GPIO_MEM_SIZE_2,
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MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_2,
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DT_APL_GPIO_MEM_SIZE_2,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3,
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CONFIG_APL_GPIO_MEM_SIZE_3,
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MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_3,
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DT_APL_GPIO_MEM_SIZE_3,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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