arch: arm64: Introduce ARM64 (AArch64) architecture
Introduce the basic ARM64 architecture support. A new CONFIG_ARM64 symbol is introduced for the new architecture and new cmake / Kconfig files are added to switch between ARM and ARM64. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Anas Nashif
parent
6f36300219
commit
1be0c05311
43 changed files with 2579 additions and 170 deletions
51
include/arch/arm/aarch64/arch.h
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51
include/arch/arm/aarch64/arch.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM64 specific kernel interface header
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*
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* This header contains the ARM64 specific kernel interface. It is
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* included by the kernel interface architecture-abstraction header
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* (include/arm/aarch64/cpu.h)
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ARCH_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ARCH_H_
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/* Add include for DTS generated information */
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#include <devicetree.h>
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#include <arch/arm/aarch64/thread.h>
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#include <arch/arm/aarch64/exc.h>
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#include <arch/arm/aarch64/irq.h>
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#include <arch/arm/aarch64/misc.h>
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#include <arch/arm/aarch64/asm_inline.h>
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#include <arch/arm/aarch64/cpu.h>
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#include <arch/arm/aarch64/sys_io.h>
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#include <arch/arm/aarch64/timer.h>
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#include <arch/common/addr_types.h>
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#include <arch/common/ffs.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Declare the STACK_ALIGN_SIZE
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*
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* Denotes the required alignment of the stack pointer on public API
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* boundaries
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*
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*/
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#define STACK_ALIGN 16
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#define STACK_ALIGN_SIZE STACK_ALIGN
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ARCH_H_ */
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21
include/arch/arm/aarch64/asm_inline.h
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21
include/arch/arm/aarch64/asm_inline.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_H_
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/*
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* The file must not be included directly
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* Include kernel.h instead
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*/
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#if defined(__GNUC__)
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#include <arch/arm/aarch64/asm_inline_gcc.h>
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#else
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#include <arch/arm/asm_inline_other.h>
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_H_ */
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65
include/arch/arm/aarch64/asm_inline_gcc.h
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65
include/arch/arm/aarch64/asm_inline_gcc.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Either public functions or macros or invoked by public functions */
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_GCC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_GCC_H_
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/*
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* The file must not be included directly
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* Include arch/cpu.h instead
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*/
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#ifndef _ASMLANGUAGE
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#include <arch/arm/aarch64/cpu.h>
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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unsigned int key;
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/*
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* Return the whole DAIF register as key but use DAIFSET to disable
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* IRQs.
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*/
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__asm__ volatile("mrs %0, daif;"
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"msr daifset, %1;"
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"isb"
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: "=r" (key)
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: "i" (DAIFSET_IRQ)
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: "memory", "cc");
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return key;
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}
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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__asm__ volatile("msr daif, %0;"
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"isb"
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:
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: "r" (key)
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: "memory", "cc");
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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/* We only check the (I)RQ bit on the DAIF register */
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return (key & DAIF_IRQ) == 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ASM_INLINE_GCC_H_ */
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59
include/arch/arm/aarch64/cpu.h
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59
include/arch/arm/aarch64/cpu.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_
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#include <sys/util.h>
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#define DAIFSET_FIQ BIT(0)
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#define DAIFSET_IRQ BIT(1)
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#define DAIFSET_ABT BIT(2)
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#define DAIFSET_DBG BIT(3)
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#define DAIF_FIQ BIT(6)
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#define DAIF_IRQ BIT(7)
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#define DAIF_ABT BIT(8)
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#define DAIF_DBG BIT(9)
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#define DAIF_MASK (0xf << 6)
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#define SPSR_MODE_EL1H (0x5)
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#define SCTLR_M_BIT BIT(0)
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#define SCTLR_A_BIT BIT(1)
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#define SCTLR_C_BIT BIT(2)
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#define SCTLR_SA_BIT BIT(3)
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#define SCTLR_I_BIT BIT(12)
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#define CPACR_EL1_FPEN_NOTRAP (0x3 << 20)
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#define SCR_EL3_NS BIT(0)
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#define SCR_EL3_IRQ BIT(1)
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#define SCR_EL3_FIQ BIT(2)
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#define SCR_EL3_EA BIT(3)
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#define SCR_EL3_RW BIT(10)
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#define HCR_EL2_FMO BIT(3)
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#define HCR_EL2_IMO BIT(4)
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#define HCR_EL2_AMO BIT(5)
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#define SPSR_EL3_h BIT(0)
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#define SPSR_EL3_TO_EL1 (0x2 << 1)
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#define __ISB() __asm__ volatile ("isb sy" : : : "memory")
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#define __DMB() __asm__ volatile ("dmb sy" : : : "memory")
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#define MODE_EL_SHIFT (0x2)
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#define MODE_EL_MASK (0x3)
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#define MODE_EL3 (0x3)
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#define MODE_EL2 (0x2)
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#define MODE_EL1 (0x1)
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#define MODE_EL0 (0x0)
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#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_ */
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44
include/arch/arm/aarch64/exc.h
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44
include/arch/arm/aarch64/exc.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cortex-A public exception handling
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*
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* ARM-specific kernel exception handling interface. Included by arm64/arch.h.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_EXC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_EXC_H_
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/* for assembler, only works with constants */
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#ifdef _ASMLANGUAGE
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#else
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct __esf {
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struct __basic_sf {
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u64_t x0;
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u64_t x1;
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u64_t x2;
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u64_t x3;
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} basic;
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};
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typedef struct __esf z_arch_esf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_EXC_H_ */
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80
include/arch/arm/aarch64/irq.h
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80
include/arch/arm/aarch64/irq.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cortex-A public interrupt handling
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*
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* ARM64-specific kernel interrupt handling interface.
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* Included by arm/aarch64/arch.h.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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GTEXT(arch_irq_enable)
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GTEXT(arch_irq_disable)
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GTEXT(arch_irq_is_enabled)
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#else
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extern void arch_irq_enable(unsigned int irq);
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extern void arch_irq_disable(unsigned int irq);
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extern int arch_irq_is_enabled(unsigned int irq);
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/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
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extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio,
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u32_t flags);
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/* All arguments must be computable by the compiler at build time.
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*
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* Z_ISR_DECLARE will populate the .intList section with the interrupt's
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* parameters, which will then be used by gen_irq_tables.py to create
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* the vector table and the software ISR table. This is all done at
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* build-time.
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*
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* We additionally set the priority in the interrupt controller at
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* runtime.
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*/
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#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \
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irq_p; \
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})
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#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
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({ \
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Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \
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z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \
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irq_p; \
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})
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/* Spurious interrupt handler. Throws an error if called */
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extern void z_irq_spurious(void *unused);
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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/* Architecture-specific common entry point for interrupts from the vector
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* table. Most likely implemented in assembly. Looks up the correct handler
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* and parameter from the _sw_isr_table and executes it.
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*/
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extern void _isr_wrapper(void);
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#endif
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_ */
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41
include/arch/arm/aarch64/misc.h
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41
include/arch/arm/aarch64/misc.h
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/*
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* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cortex-A public kernel miscellaneous
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*
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* ARM64-specific kernel miscellaneous interface. Included by
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* arm/aarch64/arch.h.
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MISC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MISC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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extern u32_t z_timer_cycle_get_32(void);
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static inline u32_t arch_k_cycle_get_32(void)
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{
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return z_timer_cycle_get_32();
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}
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static ALWAYS_INLINE void arch_nop(void)
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{
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__asm__ volatile("nop");
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_MISC_H_ */
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439
include/arch/arm/aarch64/scripts/linker.ld
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439
include/arch/arm/aarch64/scripts/linker.ld
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Cortex-A platforms.
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*/
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <devicetree.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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/* physical address of RAM */
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#ifdef CONFIG_XIP
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#define ROMABLE_REGION FLASH
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#define RAMABLE_REGION SRAM
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#else
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#define ROMABLE_REGION SRAM
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#define RAMABLE_REGION SRAM
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#endif
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#if defined(CONFIG_XIP)
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#define _DATA_IN_ROM __data_rom_start
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#else
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#define _DATA_IN_ROM
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#endif
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#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
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#define ROM_ADDR RAM_ADDR
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#else
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#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
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#endif
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#if CONFIG_FLASH_LOAD_SIZE > 0
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#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
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#else
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#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
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#endif
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#if defined(CONFIG_XIP)
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#if defined(CONFIG_IS_BOOTLOADER)
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#define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define RAM_ADDR (CONFIG_SRAM_BASE_ADDRESS + \
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(CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
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#else
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#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
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#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#endif
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#else
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#define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
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#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#endif
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/* Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
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* to make linker section alignment comply with MPU granularity.
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*/
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#if defined(CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
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_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
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#else
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/* If building without MPU support, use default 4-byte alignment. */
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_region_min_align = 4;
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#endif
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#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align); \
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. = ALIGN( 1 << LOG2CEIL(region_size))
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#else
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#define MPU_ALIGN(region_size) \
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. = ALIGN(_region_min_align)
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#endif
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MEMORY
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{
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FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
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#ifdef DT_CCM_BASE_ADDRESS
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CCM (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K
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#endif
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SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
#include <linker/rel-sections.ld>
|
||||
|
||||
/*
|
||||
* .plt and .iplt are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before text section.
|
||||
*/
|
||||
SECTION_PROLOGUE(.plt,,)
|
||||
{
|
||||
*(.plt)
|
||||
}
|
||||
|
||||
SECTION_PROLOGUE(.iplt,,)
|
||||
{
|
||||
*(.iplt)
|
||||
}
|
||||
|
||||
GROUP_START(ROMABLE_REGION)
|
||||
|
||||
_image_rom_start = ROM_ADDR;
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
|
||||
{
|
||||
|
||||
. = CONFIG_TEXT_SECTION_OFFSET;
|
||||
|
||||
#if defined(CONFIG_SW_VECTOR_RELAY)
|
||||
KEEP(*(.vector_relay_table))
|
||||
KEEP(*(".vector_relay_table.*"))
|
||||
KEEP(*(.vector_relay_handler))
|
||||
KEEP(*(".vector_relay_handler.*"))
|
||||
#endif
|
||||
|
||||
_vector_start = .;
|
||||
KEEP(*(.exc_vector_table))
|
||||
KEEP(*(".exc_vector_table.*"))
|
||||
|
||||
KEEP(*(IRQ_VECTOR_TABLE))
|
||||
|
||||
KEEP(*(.vectors))
|
||||
|
||||
KEEP(*(.openocd_dbg))
|
||||
KEEP(*(".openocd_dbg.*"))
|
||||
|
||||
_vector_end = .;
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
#ifdef CONFIG_CODE_DATA_RELOCATION
|
||||
|
||||
#include <linker_relocate.ld>
|
||||
|
||||
#endif /* CONFIG_CODE_DATA_RELOCATION */
|
||||
|
||||
SECTION_PROLOGUE(_TEXT_SECTION_NAME_2,,)
|
||||
{
|
||||
_image_text_start = .;
|
||||
*(.text)
|
||||
*(".text.*")
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
/*
|
||||
* These are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* after .gnu.linkonce.t.*
|
||||
*/
|
||||
*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
|
||||
|
||||
#include <linker/priv_stacks-text.ld>
|
||||
#include <linker/kobject-text.ld>
|
||||
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
_image_text_end = .;
|
||||
|
||||
#if defined (CONFIG_CPLUSPLUS)
|
||||
SECTION_PROLOGUE(.ARM.extab,,)
|
||||
{
|
||||
/*
|
||||
* .ARM.extab section containing exception unwinding information.
|
||||
*/
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
#endif
|
||||
|
||||
SECTION_PROLOGUE(.ARM.exidx,,)
|
||||
{
|
||||
/*
|
||||
* This section, related to stack and exception unwinding, is placed
|
||||
* explicitly to prevent it from being shared between multiple regions.
|
||||
* It must be defined for gcc to support 64-bit math and avoid
|
||||
* section overlap.
|
||||
*/
|
||||
__exidx_start = .;
|
||||
#if defined (__GCC_LINKER_CMD__)
|
||||
*(.ARM.exidx* gnu.linkonce.armexidx.*)
|
||||
#endif
|
||||
__exidx_end = .;
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
_image_rodata_start = .;
|
||||
|
||||
#include <linker/common-rom.ld>
|
||||
|
||||
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
|
||||
{
|
||||
*(.rodata)
|
||||
*(".rodata.*")
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-rodata.ld>
|
||||
#ifdef CONFIG_SOC_RODATA_LD
|
||||
#include <soc-rodata.ld>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CUSTOM_RODATA_LD
|
||||
/* Located in project source directory */
|
||||
#include <custom-rodata.ld>
|
||||
#endif
|
||||
|
||||
#include <linker/priv_stacks-rom.ld>
|
||||
#include <linker/kobject-rom.ld>
|
||||
|
||||
/*
|
||||
* For XIP images, in order to avoid the situation when __data_rom_start
|
||||
* is 32-bit aligned, but the actual data is placed right after rodata
|
||||
* section, which may not end exactly at 32-bit border, pad rodata
|
||||
* section, so __data_rom_start points at data and it is 32-bit aligned.
|
||||
*
|
||||
* On non-XIP images this may enlarge image size up to 3 bytes. This
|
||||
* generally is not an issue, since modern ROM and FLASH memory is
|
||||
* usually 4k aligned.
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
#include <linker/cplusplus-rom.ld>
|
||||
|
||||
_image_rodata_end = .;
|
||||
MPU_ALIGN(_image_rodata_end -_image_rom_start);
|
||||
_image_rom_end = .;
|
||||
|
||||
GROUP_END(ROMABLE_REGION)
|
||||
|
||||
/*
|
||||
* These are here according to 'arm-zephyr-elf-ld --verbose',
|
||||
* before data section.
|
||||
*/
|
||||
SECTION_PROLOGUE(.got,,)
|
||||
{
|
||||
*(.got.plt)
|
||||
*(.igot.plt)
|
||||
*(.got)
|
||||
*(.igot)
|
||||
}
|
||||
|
||||
GROUP_START(RAMABLE_REGION)
|
||||
|
||||
. = RAM_ADDR;
|
||||
/* Align the start of image SRAM with the
|
||||
* minimum granularity required by MPU.
|
||||
*/
|
||||
. = ALIGN(_region_min_align);
|
||||
_image_ram_start = .;
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-ram-sections.ld>
|
||||
|
||||
#if defined(CONFIG_USERSPACE)
|
||||
#define APP_SHARED_ALIGN . = ALIGN(_region_min_align);
|
||||
#define SMEM_PARTITION_ALIGN MPU_ALIGN
|
||||
|
||||
#include <app_smem.ld>
|
||||
|
||||
_app_smem_size = _app_smem_end - _app_smem_start;
|
||||
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
|
||||
#endif /* CONFIG_USERSPACE */
|
||||
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
__kernel_ram_start = .;
|
||||
|
||||
*(.bss)
|
||||
*(".bss.*")
|
||||
*(COMMON)
|
||||
*(".kernel_bss.*")
|
||||
|
||||
#ifdef CONFIG_CODE_DATA_RELOCATION
|
||||
#include <linker_sram_bss_relocate.ld>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* As memory is cleared in words only, it is simpler to ensure the BSS
|
||||
* section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
|
||||
*/
|
||||
__bss_end = ALIGN(4);
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* This section is used for non-initialized objects that
|
||||
* will not be cleared during the boot process.
|
||||
*/
|
||||
*(.noinit)
|
||||
*(".noinit.*")
|
||||
*(".kernel_noinit.*")
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-noinit.ld>
|
||||
#ifdef CONFIG_SOC_NOINIT_LD
|
||||
#include <soc-noinit.ld>
|
||||
#endif
|
||||
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
|
||||
{
|
||||
__data_ram_start = .;
|
||||
*(.data)
|
||||
*(".data.*")
|
||||
*(".kernel.*")
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-rwdata.ld>
|
||||
#ifdef CONFIG_SOC_RWDATA_LD
|
||||
#include <soc-rwdata.ld>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CUSTOM_RWDATA_LD
|
||||
/* Located in project source directory */
|
||||
#include <custom-rwdata.ld>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CODE_DATA_RELOCATION
|
||||
#include <linker_sram_data_relocate.ld>
|
||||
#endif
|
||||
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
|
||||
__data_rom_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
|
||||
#include <linker/common-ram.ld>
|
||||
#include <linker/priv_stacks.ld>
|
||||
#include <linker/kobject.ld>
|
||||
|
||||
#include <linker/priv_stacks-noinit.ld>
|
||||
|
||||
#include <linker/cplusplus-ram.ld>
|
||||
|
||||
__data_ram_end = .;
|
||||
|
||||
|
||||
/* Define linker symbols */
|
||||
|
||||
_image_ram_end = .;
|
||||
_end = .; /* end of image */
|
||||
|
||||
__kernel_ram_end = RAM_ADDR + RAM_SIZE;
|
||||
__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
|
||||
|
||||
GROUP_END(RAMABLE_REGION)
|
||||
|
||||
#ifdef CONFIG_CUSTOM_SECTIONS_LD
|
||||
/* Located in project source directory */
|
||||
#include <custom-sections.ld>
|
||||
#endif
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
#include <linker/debug-sections.ld>
|
||||
|
||||
SECTION_PROLOGUE(.ARM.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.ARM.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
|
||||
#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
|
||||
#if CONFIG_ARM_NSC_REGION_BASE_ADDRESS != 0
|
||||
#define NSC_ALIGN . = ABSOLUTE(CONFIG_ARM_NSC_REGION_BASE_ADDRESS)
|
||||
#elif defined(CONFIG_CPU_HAS_NRF_IDAU)
|
||||
/* The nRF9160 needs the NSC region to be at the end of a 32 kB region. */
|
||||
#define NSC_ALIGN . = ALIGN(0x8000) - (1 << LOG2CEIL(__sg_size))
|
||||
#else
|
||||
#define NSC_ALIGN . = ALIGN(4)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_NRF_IDAU
|
||||
#define NSC_ALIGN_END . = ALIGN(0x8000)
|
||||
#else
|
||||
#define NSC_ALIGN_END . = ALIGN(4)
|
||||
#endif
|
||||
|
||||
SECTION_PROLOGUE(.gnu.sgstubs,,)
|
||||
{
|
||||
NSC_ALIGN;
|
||||
__sg_start = .;
|
||||
/* No input section necessary, since the Secure Entry Veneers are
|
||||
automatically placed after the .gnu.sgstubs output section. */
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
__sg_end = .;
|
||||
__sg_size = __sg_end - __sg_start;
|
||||
NSC_ALIGN_END;
|
||||
__nsc_size = . - __sg_start;
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_NRF_IDAU
|
||||
ASSERT(1 << LOG2CEIL(0x8000 - (__sg_start % 0x8000))
|
||||
== (0x8000 - (__sg_start % 0x8000))
|
||||
&& (0x8000 - (__sg_start % 0x8000)) >= 32
|
||||
&& (0x8000 - (__sg_start % 0x8000)) <= 4096,
|
||||
"The Non-Secure Callable region size must be a power of 2 \
|
||||
between 32 and 4096 bytes.")
|
||||
#endif
|
||||
#endif /* CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS */
|
||||
|
||||
/* Must be last in romable region */
|
||||
SECTION_PROLOGUE(.last_section,(NOLOAD),)
|
||||
{
|
||||
} GROUP_LINK_IN(ROMABLE_REGION)
|
||||
|
||||
/* To provide the image size as a const expression,
|
||||
* calculate this value here. */
|
||||
_flash_used = LOADADDR(.last_section) - _image_rom_start;
|
||||
|
||||
}
|
||||
162
include/arch/arm/aarch64/sys_io.h
Normal file
162
include/arch/arm/aarch64/sys_io.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Wind River Systems, Inc.
|
||||
* Copyright (c) 2017, Oticon A/S
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* "Arch" bit manipulation functions in non-arch-specific C code (uses some
|
||||
* gcc builtins)
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_SYS_IO_H_
|
||||
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_SYS_IO_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <zephyr/types.h>
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Memory mapped registers I/O functions */
|
||||
|
||||
static ALWAYS_INLINE u8_t sys_read8(mem_addr_t addr)
|
||||
{
|
||||
u8_t val = *(volatile u8_t *)addr;
|
||||
|
||||
__DMB();
|
||||
return val;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE void sys_write8(u8_t data, mem_addr_t addr)
|
||||
{
|
||||
__DMB();
|
||||
*(volatile u8_t *)addr = data;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE u16_t sys_read16(mem_addr_t addr)
|
||||
{
|
||||
u16_t val = *(volatile u16_t *)addr;
|
||||
|
||||
__DMB();
|
||||
return val;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE void sys_write16(u16_t data, mem_addr_t addr)
|
||||
{
|
||||
__DMB();
|
||||
*(volatile u16_t *)addr = data;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE u32_t sys_read32(mem_addr_t addr)
|
||||
{
|
||||
u32_t val = *(volatile u32_t *)addr;
|
||||
|
||||
__DMB();
|
||||
return val;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE void sys_write32(u32_t data, mem_addr_t addr)
|
||||
{
|
||||
__DMB();
|
||||
*(volatile u32_t *)addr = data;
|
||||
}
|
||||
|
||||
/* Memory bit manipulation functions */
|
||||
|
||||
static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
u32_t temp = *(volatile u32_t *)addr;
|
||||
|
||||
*(volatile u32_t *)addr = temp | (1 << bit);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
u32_t temp = *(volatile u32_t *)addr;
|
||||
|
||||
*(volatile u32_t *)addr = temp & ~(1 << bit);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
u32_t temp = *(volatile u32_t *)addr;
|
||||
|
||||
return temp & (1 << bit);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
/* Doing memory offsets in terms of 32-bit values to prevent
|
||||
* alignment issues
|
||||
*/
|
||||
sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = sys_test_bit(addr, bit);
|
||||
sys_set_bit(addr, bit);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = sys_test_bit(addr, bit);
|
||||
sys_clear_bit(addr, bit);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = sys_bitfield_test_bit(addr, bit);
|
||||
sys_bitfield_set_bit(addr, bit);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE
|
||||
int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = sys_bitfield_test_bit(addr, bit);
|
||||
sys_bitfield_clear_bit(addr, bit);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_SYS_IO_H_ */
|
||||
22
include/arch/arm/aarch64/syscall.h
Normal file
22
include/arch/arm/aarch64/syscall.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief ARM specific syscall header
|
||||
*
|
||||
* This header contains the ARM specific syscall interface. It is
|
||||
* included by the syscall interface architecture-abstraction header
|
||||
* (include/arch/aarch64/syscall.h)
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_ARCH_AARCH64_ARM_SYSCALL_H_
|
||||
#define ZEPHYR_INCLUDE_ARCH_AARCH64_ARM_SYSCALL_H_
|
||||
|
||||
#define _SVC_CALL_CONTEXT_SWITCH 0
|
||||
#define _SVC_CALL_IRQ_OFFLOAD 1
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_SYSCALL_H_ */
|
||||
53
include/arch/arm/aarch64/thread.h
Normal file
53
include/arch/arm/aarch64/thread.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Per-arch thread definition
|
||||
*
|
||||
* This file contains definitions for
|
||||
*
|
||||
* struct _thread_arch
|
||||
* struct _callee_saved
|
||||
*
|
||||
* necessary to instantiate instances of struct k_thread.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_THREAD_H_
|
||||
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_THREAD_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <zephyr/types.h>
|
||||
|
||||
struct _callee_saved {
|
||||
u64_t x19;
|
||||
u64_t x20;
|
||||
u64_t x21;
|
||||
u64_t x22;
|
||||
u64_t x23;
|
||||
u64_t x24;
|
||||
u64_t x25;
|
||||
u64_t x26;
|
||||
u64_t x27;
|
||||
u64_t x28;
|
||||
u64_t x29; /* FP */
|
||||
u64_t x30; /* LR */
|
||||
u64_t spsr;
|
||||
u64_t elr;
|
||||
u64_t sp;
|
||||
};
|
||||
|
||||
typedef struct _callee_saved _callee_saved_t;
|
||||
|
||||
struct _thread_arch {
|
||||
u32_t swap_return_value;
|
||||
};
|
||||
|
||||
typedef struct _thread_arch _thread_arch_t;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_THREAD_H_ */
|
||||
61
include/arch/arm/aarch64/timer.h
Normal file
61
include/arch/arm/aarch64/timer.h
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_TIMER_H_
|
||||
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_TIMER_H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <drivers/timer/arm_arch_timer.h>
|
||||
#include <zephyr/types.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ARM_ARCH_TIMER_IRQ ((ARM_TIMER_VIRTUAL_IRQ + 1) << 8)
|
||||
#define CNTV_CTL_ENABLE ((1) << 0)
|
||||
|
||||
|
||||
static ALWAYS_INLINE void arm_arch_timer_set_compare(u64_t val)
|
||||
{
|
||||
__asm__ volatile("msr cntv_cval_el0, %0\n\t"
|
||||
: : "r" (val) : "memory");
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
|
||||
{
|
||||
u32_t cntv_ctl;
|
||||
|
||||
__asm__ volatile("mrs %0, cntv_ctl_el0\n\t"
|
||||
: "=r" (cntv_ctl) : : "memory");
|
||||
|
||||
if (enable)
|
||||
cntv_ctl |= CNTV_CTL_ENABLE;
|
||||
else
|
||||
cntv_ctl &= ~CNTV_CTL_ENABLE;
|
||||
|
||||
__asm__ volatile("msr cntv_ctl_el0, %0\n\t"
|
||||
: : "r" (cntv_ctl) : "memory");
|
||||
}
|
||||
|
||||
static ALWAYS_INLINE u64_t arm_arch_timer_count(void)
|
||||
{
|
||||
u64_t cntvct_el0;
|
||||
|
||||
__asm__ volatile("mrs %0, cntvct_el0\n\t"
|
||||
: "=r" (cntvct_el0) : : "memory");
|
||||
|
||||
return cntvct_el0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_TIMER_H_ */
|
||||
|
|
@ -13,6 +13,8 @@
|
|||
|
||||
#if defined(CONFIG_X86)
|
||||
#include <arch/x86/arch.h>
|
||||
#elif defined(CONFIG_ARM64)
|
||||
#include <arch/arm/aarch64/arch.h>
|
||||
#elif defined(CONFIG_ARM)
|
||||
#include <arch/arm/aarch32/arch.h>
|
||||
#elif defined(CONFIG_ARC)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue