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soc/openisa: enable the C extension

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According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-07-01 10:03:11 +02:00 • committed by Anas Nashif
commit 18ddac4acf
2 changed files with 3 additions and 3 deletions
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4
dts/riscv/openisa/rv32m1.dtsi
View file

@ -23,14 +23,14 @@
cpu@0 { cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "openisa,ri5cy", "riscv"; compatible = "openisa,ri5cy", "riscv";
riscv,isa = "rv32ima_zicsr_zifencei"; riscv,isa = "rv32imc_zicsr_zifencei";
reg = <0>; reg = <0>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "openisa,zero-ri5cy", "riscv"; compatible = "openisa,zero-ri5cy", "riscv";
riscv,isa = "rv32ima_zicsr_zifencei"; riscv,isa = "rv32imc_zicsr_zifencei";
reg = <1>; reg = <1>;
}; };
}; };

2
soc/openisa/rv32m1/Kconfig
View file

@ -17,6 +17,6 @@ config SOC_OPENISA_RV32M1
select BUILD_OUTPUT_HEX select BUILD_OUTPUT_HEX
select RISCV_ISA_RV32I select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI select RISCV_ISA_EXT_ZIFENCEI