diff --git a/dts/riscv/openisa/rv32m1.dtsi b/dts/riscv/openisa/rv32m1.dtsi
index cb234eba998..d514cf94642 100644
--- a/dts/riscv/openisa/rv32m1.dtsi
+++ b/dts/riscv/openisa/rv32m1.dtsi
@@ -23,14 +23,14 @@
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "openisa,ri5cy", "riscv";
-			riscv,isa = "rv32ima_zicsr_zifencei";
+			riscv,isa = "rv32imc_zicsr_zifencei";
 			reg = <0>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "openisa,zero-ri5cy", "riscv";
-			riscv,isa = "rv32ima_zicsr_zifencei";
+			riscv,isa = "rv32imc_zicsr_zifencei";
 			reg = <1>;
 		};
 	};
diff --git a/soc/openisa/rv32m1/Kconfig b/soc/openisa/rv32m1/Kconfig
index 21fe5d9297d..199d13ba744 100644
--- a/soc/openisa/rv32m1/Kconfig
+++ b/soc/openisa/rv32m1/Kconfig
@@ -17,6 +17,6 @@ config SOC_OPENISA_RV32M1
 	select BUILD_OUTPUT_HEX
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
-	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI