From 18ddac4acf36e967e13b0ab058fab9c5a4622813 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Mon, 1 Jul 2024 10:03:11 +0200 Subject: [PATCH] soc/openisa: enable the `C` extension According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C extension, and doesn't support the A extension. Apply fixes accordingly. Signed-off-by: Filip Kokosinski --- dts/riscv/openisa/rv32m1.dtsi | 4 ++-- soc/openisa/rv32m1/Kconfig | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/dts/riscv/openisa/rv32m1.dtsi b/dts/riscv/openisa/rv32m1.dtsi index cb234eba998..d514cf94642 100644 --- a/dts/riscv/openisa/rv32m1.dtsi +++ b/dts/riscv/openisa/rv32m1.dtsi @@ -23,14 +23,14 @@ cpu@0 { device_type = "cpu"; compatible = "openisa,ri5cy", "riscv"; - riscv,isa = "rv32ima_zicsr_zifencei"; + riscv,isa = "rv32imc_zicsr_zifencei"; reg = <0>; }; cpu@1 { device_type = "cpu"; compatible = "openisa,zero-ri5cy", "riscv"; - riscv,isa = "rv32ima_zicsr_zifencei"; + riscv,isa = "rv32imc_zicsr_zifencei"; reg = <1>; }; }; diff --git a/soc/openisa/rv32m1/Kconfig b/soc/openisa/rv32m1/Kconfig index 21fe5d9297d..199d13ba744 100644 --- a/soc/openisa/rv32m1/Kconfig +++ b/soc/openisa/rv32m1/Kconfig @@ -17,6 +17,6 @@ config SOC_OPENISA_RV32M1 select BUILD_OUTPUT_HEX select RISCV_ISA_RV32I select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI