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drivers: edma: allow transfer descriptors to be placed in SRAM

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SOCs using the EDMA IP that supported caching must locate EDMA transfer
control descriptors (TCDs) in non cacheable memory. For M7 cores, this
can simply use the "nocache" section. For M4 cores, where the nocache
section does not exist, the chosen SRAM section must be a tightly
coupled memory block which cannot be cached. Add a note to all boards
with M4 SOCs that support caching explaining this issue, and enable EDMA
driver to locate TCDs in SRAM.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-04-19 18:11:43 -05:00 • committed by Carles Cufí
commit 17d9bea474
6 changed files with 48 additions and 1 deletions
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6
boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts
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@ -23,6 +23,12 @@
};
chosen {
/*
* Note: when using DMA, the SRAM region must be set to
* a memory region that is not cached by the chip. If the chosen
* sram region is changed and DMA is in use, you will
* encounter issues!
*/
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;