diff --git a/boards/arm/frdm_k82f/frdm_k82f.dts b/boards/arm/frdm_k82f/frdm_k82f.dts
index 64807fce8df..6211694611f 100644
--- a/boards/arm/frdm_k82f/frdm_k82f.dts
+++ b/boards/arm/frdm_k82f/frdm_k82f.dts
@@ -27,6 +27,12 @@
 	};
 
 	chosen {
+		/*
+		 * Note: when using DMA, the SRAM region must be set to
+		 * a memory region that is not cached by the chip. If the chosen
+		 * sram region is changed and DMA is in use, you will
+		 * encounter issues!
+		 */
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
index 249e03bf1d2..729a827e9a4 100644
--- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
+++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
@@ -14,6 +14,12 @@
 	compatible = "nxp,mimxrt1166";
 
 	chosen {
+		/*
+		 * Note: when using DMA, the SRAM region must be set to
+		 * a memory region that is not cached by the chip. If the chosen
+		 * sram region is changed and DMA is in use, you will
+		 * encounter issues!
+		 */
 		zephyr,sram = &sram1;
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
@@ -91,3 +97,7 @@
 &gpt_hw_timer {
 	status = "okay";
 };
+
+&edma_lpsr0 {
+	status = "okay";
+};
diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts
index 4c7b480702a..83152956a54 100644
--- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts
+++ b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts
@@ -14,6 +14,12 @@
 	compatible = "nxp,mimxrt1176";
 
 	chosen {
+		/*
+		 * Note: when using DMA, the SRAM region must be set to
+		 * a memory region that is not cached by the chip. If the chosen
+		 * sram region is changed and DMA is in use, you will
+		 * encounter issues!
+		 */
 		zephyr,sram = &sram1;
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
@@ -95,3 +101,7 @@
 &sai1 {
 	status = "okay";
 };
+
+&edma_lpsr0 {
+	status = "okay";
+};
diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts
index 7f939edc804..c9bcfce2cba 100644
--- a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts
+++ b/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts
@@ -23,6 +23,12 @@
 	};
 
 	chosen {
+		/*
+		 * Note: when using DMA, the SRAM region must be set to
+		 * a memory region that is not cached by the chip. If the chosen
+		 * sram region is changed and DMA is in use, you will
+		 * encounter issues!
+		 */
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
diff --git a/boards/arm/twr_ke18f/twr_ke18f.dts b/boards/arm/twr_ke18f/twr_ke18f.dts
index b5a9e572b5c..b84c75660b1 100644
--- a/boards/arm/twr_ke18f/twr_ke18f.dts
+++ b/boards/arm/twr_ke18f/twr_ke18f.dts
@@ -35,6 +35,12 @@
 	};
 
 	chosen {
+		/*
+		 * Note: when using DMA, the SRAM region must be set to
+		 * a memory region that is not cached by the chip. If the chosen
+		 * sram region is changed and DMA is in use, you will
+		 * encounter issues!
+		 */
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c
index f974e06fcf3..f21d7acfb2d 100644
--- a/drivers/dma/dma_mcux_edma.c
+++ b/drivers/dma/dma_mcux_edma.c
@@ -47,7 +47,16 @@ struct dma_mcux_edma_config {
 #elif defined(CONFIG_NOCACHE_MEMORY)
 #define EDMA_TCDPOOL_CACHE_ATTR __nocache
 #else
-#error tcdpool could not be located in cacheable memory, a requirement for proper EDMA operation.
+/*
+ * Note: the TCD pool *must* be in non cacheable memory. All of the NXP SOCs
+ * that support caching memory have their default SRAM regions defined as a
+ * non cached memory region, but if the default SRAM region is changed EDMA
+ * TCD pools would be moved to cacheable memory, resulting in DMA cache
+ * coherency issues.
+ */
+
+#define EDMA_TCDPOOL_CACHE_ATTR
+
 #endif /* CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS */
 
 #else /* CONFIG_HAS_MCUX_CACHE */