arch: nios2: update nios2 softcpu image
Update nios2 softcpu image which supports additional soft IP's like I2C, SPI, SGDMA, QSPI, SysID, etc... Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This commit is contained in:
parent
589a5dad17
commit
151f431efa
11 changed files with 10448 additions and 1324 deletions
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@ -1,16 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<pin_planner>
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<pin_info>
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<pin name="mem_ck[0]" source="Assignments" >
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</pin>
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<pin name="mem_ck_n[0]" source="Assignments" >
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</pin>
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</pin_info>
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<buses>
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</buses>
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<group_file_association>
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</group_file_association>
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<pin_planner_file_specifies>
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</pin_planner_file_specifies>
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</pin_planner>
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@ -41,7 +41,7 @@ set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M50DAF484C6GES
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
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set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
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set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
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@ -52,7 +52,7 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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@ -74,7 +74,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name SEED 2
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set_global_assignment -name SEED 16
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set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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@ -396,4 +396,17 @@ set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v
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set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip
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set_global_assignment -name SDC_FILE ghrd_timing.sdc
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set_location_assignment PIN_A10 -to i2c_scl
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set_location_assignment PIN_B15 -to i2c_sda
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set_location_assignment PIN_B7 -to spi_sclk
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set_location_assignment PIN_A6 -to spi_miso
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set_location_assignment PIN_C8 -to spi_mosi
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set_location_assignment PIN_C7 -to spi_ssn
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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File diff suppressed because one or more lines are too long
Binary file not shown.
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File diff suppressed because one or more lines are too long
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@ -1,11 +1,36 @@
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module ghrd_10m50da_top (
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//Clock and Reset
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input wire clk_50,
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//input wire clk_ddr3_100_p,
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input wire fpga_reset_n,
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//QSPI
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// output wire qspi_clk,
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// inout wire[3:0] qspi_io,
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// output wire qspi_csn,
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output wire qspi_clk,
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inout wire[3:0] qspi_io,
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output wire qspi_csn,
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//ddr3
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//output wire [13:0] mem_a,
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//output wire [2:0] mem_ba,
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//inout wire [0:0] mem_ck,
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//inout wire [0:0] mem_ck_n,
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//output wire [0:0] mem_cke,
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//output wire [0:0] mem_cs_n,
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//output wire [0:0] mem_dm,
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//output wire [0:0] mem_ras_n,
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//output wire [0:0] mem_cas_n,
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//output wire [0:0] mem_we_n,
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//output wire mem_reset_n,
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///inout wire [7:0] mem_dq,
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//inout wire [0:0] mem_dqs,
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//inout wire [0:0] mem_dqs_n,
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//output wire [0:0] mem_odt,
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//i2c
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inout wire i2c_sda,
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inout wire i2c_scl,
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//spi
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input wire spi_miso,
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output wire spi_mosi,
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output wire spi_sclk,
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output wire spi_ssn,
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//16550 UART
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input wire uart_rx,
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output wire uart_tx,
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@ -14,20 +39,72 @@ module ghrd_10m50da_top (
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//Heart-beat counter
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reg [25:0] heart_beat_cnt;
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//DDR3 interface assignments
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//wire local_init_done;
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//wire local_cal_success;
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//wire local_cal_fail;
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//i2c interface
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wire i2c_serial_sda_in ;
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wire i2c_serial_scl_in ;
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wire i2c_serial_sda_oe ;
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wire i2c_serial_scl_oe ;
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assign i2c_serial_scl_in = i2c_scl;
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assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
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assign i2c_serial_sda_in = i2c_sda;
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assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
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//assign system_resetn = fpga_reset_n & local_init_done;
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// SoC sub-system module
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ghrd_10m50da ghrd_10m50da_inst (
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.clk_clk (clk_50),
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.reset_reset_n (fpga_reset_n),
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// .ext_flash_flash_dataout_conduit_dataout (qspi_io),
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// .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk),
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// .ext_flash_flash_ncs_conduit_ncs (qspi_csn),
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.clk_clk (clk_50),
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//.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
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.reset_reset_n (fpga_reset_n),
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//.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
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.ext_flash_qspi_pins_data (qspi_io),
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.ext_flash_qspi_pins_dclk (qspi_clk),
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.ext_flash_qspi_pins_ncs (qspi_csn),
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//.memory_mem_a (mem_a[12:0] ), // memory.mem_a
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//.memory_mem_ba (mem_ba ), // .mem_ba
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//.memory_mem_ck (mem_ck ), // .mem_ck
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//.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
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//.memory_mem_cke (mem_cke ), // .mem_cke
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//.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
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//.memory_mem_dm (mem_dm ), // .mem_dm
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//.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
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//.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
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//.memory_mem_we_n (mem_we_n ), // .mem_we_n
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//.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
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//.memory_mem_dq (mem_dq ), // .mem_dq
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//.memory_mem_dqs (mem_dqs ), // .mem_dqs
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//.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
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//.memory_mem_odt (mem_odt ), // .mem_odt
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//.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
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//.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
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//.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
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//i2c
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.i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
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.i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
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.i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
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.i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
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//spi
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.spi_0_external_MISO (spi_miso), // spi_0_external.MISO
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.spi_0_external_MOSI (spi_mosi), // .MOSI
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.spi_0_external_SCLK (spi_sclk), // .SCLK
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.spi_0_external_SS_n (spi_ssn), // .SS_n
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//pio
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.led_external_connection_export (user_led[3:0]),
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//16550 UART
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.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
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.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
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.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
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);
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);
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//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
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//assign mem_a[13] = 1'b0;
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//Heart beat by 50MHz clock
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always @(posedge clk_50 or negedge fpga_reset_n)
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else
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heart_beat_cnt <= heart_beat_cnt + 1'b1;
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assign user_led = {4'hf,heart_beat_cnt[25]};
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assign user_led[4] = heart_beat_cnt[25];
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endmodule
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@ -10,11 +10,19 @@ set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_
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set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
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set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
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create_clock -name {CLK_50} -period 20.000 {clk_50}
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create_clock -name {clk_50} -period 20.000 {clk_50}
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set_false_path -to [get_ports {user_led[*]}]
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set_false_path -to [get_ports {fpga_reset_n}]
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set_false_path -from [get_ports {fpga_reset_n}]
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derive_clock_uncertainty
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# QSPI interface
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
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set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
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set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
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# UART
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set_false_path -from * -to [get_ports {uart_tx}]
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File diff suppressed because it is too large
Load diff
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@ -4,7 +4,7 @@
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* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
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* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
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*
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* Generated: Wed Jun 08 19:21:55 MYT 2016
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* Generated: Tue Dec 05 14:42:02 SGT 2017
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*/
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/*
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*
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*/
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#define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
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#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108864
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#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
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#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
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#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
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#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
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#define ONCHIP_MEMORY2_0_REGION_SPAN 167904
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#define ONCHIP_MEMORY2_0_REGION_SPAN 131040
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#define RESET_REGION_BASE 0x0
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#define RESET_REGION_SPAN 32
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* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
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* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
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*
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* Generated: Wed Jun 08 19:18:29 MYT 2016
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* Generated: Tue Dec 05 14:41:17 SGT 2017
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*/
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/*
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#define ALT_CPU_CPU_ID_SIZE 1
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#define ALT_CPU_CPU_ID_VALUE 0x00000000
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#define ALT_CPU_CPU_IMPLEMENTATION "fast"
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#define ALT_CPU_DATA_ADDR_WIDTH 0x17
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#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
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#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
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#define ALT_CPU_DCACHE_LINE_SIZE 32
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#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
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#define ALT_CPU_ICACHE_SIZE 4096
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#define ALT_CPU_INITDA_SUPPORTED
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#define ALT_CPU_INST_ADDR_WIDTH 0x17
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#define ALT_CPU_INST_ADDR_WIDTH 0x1c
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#define ALT_CPU_NAME "nios2_gen2_0"
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#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
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#define ALT_CPU_OCI_VERSION 1
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#define NIOS2_CPU_ID_SIZE 1
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#define NIOS2_CPU_ID_VALUE 0x00000000
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#define NIOS2_CPU_IMPLEMENTATION "fast"
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#define NIOS2_DATA_ADDR_WIDTH 0x17
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#define NIOS2_DATA_ADDR_WIDTH 0x1c
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#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
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#define NIOS2_DCACHE_LINE_SIZE 32
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#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
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#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
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#define NIOS2_ICACHE_SIZE 4096
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#define NIOS2_INITDA_SUPPORTED
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#define NIOS2_INST_ADDR_WIDTH 0x17
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#define NIOS2_INST_ADDR_WIDTH 0x1c
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#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
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#define NIOS2_OCI_VERSION 1
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#define NIOS2_RESET_ADDR 0x00000000
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*/
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#define __ALTERA_16550_UART
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#define __ALTERA_AVALON_I2C
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#define __ALTERA_AVALON_JTAG_UART
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#define __ALTERA_AVALON_ONCHIP_MEMORY2
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#define __ALTERA_AVALON_PIO
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#define __ALTERA_AVALON_SPI
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#define __ALTERA_AVALON_SYSID_QSYS
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#define __ALTERA_AVALON_TIMER
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#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER2
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#define __ALTERA_MSGDMA
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#define __ALTERA_NIOS2_GEN2
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#define __ALTERA_ONCHIP_FLASH
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*/
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#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
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#define A_16550_UART_0_BASE 0x440000
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#define A_16550_UART_0_BASE 0x100000
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#define A_16550_UART_0_FIFO_DEPTH 64
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#define A_16550_UART_0_FIFO_MODE 1
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#define A_16550_UART_0_FIO_HWFC 0
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#define A_16550_UART_0_TYPE "altera_16550_uart"
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/*
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* ext_flash_avl_csr configuration
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*
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*/
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#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller2
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#define EXT_FLASH_AVL_CSR_BASE 0x100240
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#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512"
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#define EXT_FLASH_AVL_CSR_IRQ 6
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#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define EXT_FLASH_AVL_CSR_IS_EPCS 0
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#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr"
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#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024
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#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256
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#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536
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#define EXT_FLASH_AVL_CSR_SPAN 64
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#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096
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#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller2"
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/*
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* ext_flash_avl_mem configuration
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*
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*/
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#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller2
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#define EXT_FLASH_AVL_MEM_BASE 0x8000000
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#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512"
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#define EXT_FLASH_AVL_MEM_IRQ -1
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#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define EXT_FLASH_AVL_MEM_IS_EPCS 0
|
||||
#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem"
|
||||
#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024
|
||||
#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256
|
||||
#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536
|
||||
#define EXT_FLASH_AVL_MEM_SPAN 67108864
|
||||
#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096
|
||||
#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller2"
|
||||
|
||||
|
||||
/*
|
||||
* hal configuration
|
||||
*
|
||||
|
@ -217,6 +263,23 @@
|
|||
#define ALT_TIMESTAMP_CLK none
|
||||
|
||||
|
||||
/*
|
||||
* i2c_0 configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_i2c_0 altera_avalon_i2c
|
||||
#define I2C_0_BASE 0x100200
|
||||
#define I2C_0_FIFO_DEPTH 16
|
||||
#define I2C_0_FREQ 50000000
|
||||
#define I2C_0_IRQ 4
|
||||
#define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define I2C_0_NAME "/dev/i2c_0"
|
||||
#define I2C_0_SPAN 64
|
||||
#define I2C_0_TYPE "altera_avalon_i2c"
|
||||
#define I2C_0_USE_AV_ST 0
|
||||
|
||||
|
||||
/*
|
||||
* jtag_uart_0 configuration
|
||||
*
|
||||
|
@ -235,6 +298,109 @@
|
|||
#define JTAG_UART_0_WRITE_THRESHOLD 8
|
||||
|
||||
|
||||
/*
|
||||
* led configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_led altera_avalon_pio
|
||||
#define LED_BASE 0x1002e0
|
||||
#define LED_BIT_CLEARING_EDGE_REGISTER 0
|
||||
#define LED_BIT_MODIFYING_OUTPUT_REGISTER 0
|
||||
#define LED_CAPTURE 0
|
||||
#define LED_DATA_WIDTH 4
|
||||
#define LED_DO_TEST_BENCH_WIRING 0
|
||||
#define LED_DRIVEN_SIM_VALUE 0
|
||||
#define LED_EDGE_TYPE "NONE"
|
||||
#define LED_FREQ 50000000
|
||||
#define LED_HAS_IN 0
|
||||
#define LED_HAS_OUT 1
|
||||
#define LED_HAS_TRI 0
|
||||
#define LED_IRQ -1
|
||||
#define LED_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define LED_IRQ_TYPE "NONE"
|
||||
#define LED_NAME "/dev/led"
|
||||
#define LED_RESET_VALUE 0
|
||||
#define LED_SPAN 16
|
||||
#define LED_TYPE "altera_avalon_pio"
|
||||
|
||||
|
||||
/*
|
||||
* msgdma_0_csr configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_msgdma_0_csr altera_msgdma
|
||||
#define MSGDMA_0_CSR_BASE 0x1002c0
|
||||
#define MSGDMA_0_CSR_BURST_ENABLE 1
|
||||
#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 1
|
||||
#define MSGDMA_0_CSR_CHANNEL_ENABLE 0
|
||||
#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_CSR_CHANNEL_WIDTH 8
|
||||
#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32
|
||||
#define MSGDMA_0_CSR_DATA_WIDTH 32
|
||||
#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128
|
||||
#define MSGDMA_0_CSR_DMA_MODE 0
|
||||
#define MSGDMA_0_CSR_ENHANCED_FEATURES 0
|
||||
#define MSGDMA_0_CSR_ERROR_ENABLE 0
|
||||
#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_CSR_ERROR_WIDTH 8
|
||||
#define MSGDMA_0_CSR_IRQ 3
|
||||
#define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define MSGDMA_0_CSR_MAX_BURST_COUNT 2
|
||||
#define MSGDMA_0_CSR_MAX_BYTE 1024
|
||||
#define MSGDMA_0_CSR_MAX_STRIDE 1
|
||||
#define MSGDMA_0_CSR_NAME "/dev/msgdma_0_csr"
|
||||
#define MSGDMA_0_CSR_PACKET_ENABLE 0
|
||||
#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
|
||||
#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
|
||||
#define MSGDMA_0_CSR_RESPONSE_PORT 2
|
||||
#define MSGDMA_0_CSR_SPAN 32
|
||||
#define MSGDMA_0_CSR_STRIDE_ENABLE 0
|
||||
#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_CSR_TRANSFER_TYPE "Aligned Accesses"
|
||||
#define MSGDMA_0_CSR_TYPE "altera_msgdma"
|
||||
|
||||
|
||||
/*
|
||||
* msgdma_0_descriptor_slave configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_msgdma_0_descriptor_slave altera_msgdma
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 1
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 1
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ -1
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_NAME "/dev/msgdma_0_descriptor_slave"
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE "Aligned Accesses"
|
||||
#define MSGDMA_0_DESCRIPTOR_SLAVE_TYPE "altera_msgdma"
|
||||
|
||||
|
||||
/*
|
||||
* onchip_flash_0_csr configuration
|
||||
*
|
||||
|
@ -320,12 +486,59 @@
|
|||
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
|
||||
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
|
||||
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
|
||||
#define ONCHIP_MEMORY2_0_SIZE_VALUE 167936
|
||||
#define ONCHIP_MEMORY2_0_SPAN 167936
|
||||
#define ONCHIP_MEMORY2_0_SIZE_VALUE 131072
|
||||
#define ONCHIP_MEMORY2_0_SPAN 131072
|
||||
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
|
||||
#define ONCHIP_MEMORY2_0_WRITABLE 1
|
||||
|
||||
|
||||
/*
|
||||
* spi_0 configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
|
||||
#define SPI_0_BASE 0x100280
|
||||
#define SPI_0_CLOCKMULT 1
|
||||
#define SPI_0_CLOCKPHASE 1
|
||||
#define SPI_0_CLOCKPOLARITY 0
|
||||
#define SPI_0_CLOCKUNITS "Hz"
|
||||
#define SPI_0_DATABITS 8
|
||||
#define SPI_0_DATAWIDTH 16
|
||||
#define SPI_0_DELAYMULT "1.0E-9"
|
||||
#define SPI_0_DELAYUNITS "ns"
|
||||
#define SPI_0_EXTRADELAY 0
|
||||
#define SPI_0_INSERT_SYNC 0
|
||||
#define SPI_0_IRQ 5
|
||||
#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
||||
#define SPI_0_ISMASTER 1
|
||||
#define SPI_0_LSBFIRST 0
|
||||
#define SPI_0_NAME "/dev/spi_0"
|
||||
#define SPI_0_NUMSLAVES 1
|
||||
#define SPI_0_PREFIX "spi_"
|
||||
#define SPI_0_SPAN 32
|
||||
#define SPI_0_SYNC_REG_DEPTH 2
|
||||
#define SPI_0_TARGETCLOCK 128000u
|
||||
#define SPI_0_TARGETSSDELAY "0.0"
|
||||
#define SPI_0_TYPE "altera_avalon_spi"
|
||||
|
||||
|
||||
/*
|
||||
* sysid configuration
|
||||
*
|
||||
*/
|
||||
|
||||
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
|
||||
#define SYSID_BASE 0x100300
|
||||
#define SYSID_ID 0
|
||||
#define SYSID_IRQ -1
|
||||
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
|
||||
#define SYSID_NAME "/dev/sysid"
|
||||
#define SYSID_SPAN 8
|
||||
#define SYSID_TIMESTAMP 1512455752
|
||||
#define SYSID_TYPE "altera_avalon_sysid_qsys"
|
||||
|
||||
|
||||
/*
|
||||
* timer_0 configuration
|
||||
*
|
||||
|
@ -333,7 +546,7 @@
|
|||
|
||||
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
|
||||
#define TIMER_0_ALWAYS_RUN 0
|
||||
#define TIMER_0_BASE 0x440200
|
||||
#define TIMER_0_BASE 0x1002a0
|
||||
#define TIMER_0_COUNTER_SIZE 32
|
||||
#define TIMER_0_FIXED_PERIOD 0
|
||||
#define TIMER_0_FREQ 50000000
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue