arch: nios2: update nios2 softcpu image

Update nios2 softcpu image which supports additional
soft IP's like I2C, SPI, SGDMA, QSPI, SysID, etc...

Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This commit is contained in:
Ramakrishna Pallala 2017-12-11 07:48:35 -05:00 committed by Anas Nashif
commit 151f431efa
11 changed files with 10448 additions and 1324 deletions

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@ -1,16 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
<pin name="mem_ck[0]" source="Assignments" >
</pin>
<pin name="mem_ck_n[0]" source="Assignments" >
</pin>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

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@ -41,7 +41,7 @@ set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
@ -52,7 +52,7 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
@ -74,7 +74,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name SEED 2
set_global_assignment -name SEED 16
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
@ -396,4 +396,17 @@ set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v
set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip
set_global_assignment -name SDC_FILE ghrd_timing.sdc
set_location_assignment PIN_A10 -to i2c_scl
set_location_assignment PIN_B15 -to i2c_sda
set_location_assignment PIN_B7 -to spi_sclk
set_location_assignment PIN_A6 -to spi_miso
set_location_assignment PIN_C8 -to spi_mosi
set_location_assignment PIN_C7 -to spi_ssn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n
set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp
set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@ -1,11 +1,36 @@
module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
//input wire clk_ddr3_100_p,
input wire fpga_reset_n,
//QSPI
// output wire qspi_clk,
// inout wire[3:0] qspi_io,
// output wire qspi_csn,
output wire qspi_clk,
inout wire[3:0] qspi_io,
output wire qspi_csn,
//ddr3
//output wire [13:0] mem_a,
//output wire [2:0] mem_ba,
//inout wire [0:0] mem_ck,
//inout wire [0:0] mem_ck_n,
//output wire [0:0] mem_cke,
//output wire [0:0] mem_cs_n,
//output wire [0:0] mem_dm,
//output wire [0:0] mem_ras_n,
//output wire [0:0] mem_cas_n,
//output wire [0:0] mem_we_n,
//output wire mem_reset_n,
///inout wire [7:0] mem_dq,
//inout wire [0:0] mem_dqs,
//inout wire [0:0] mem_dqs_n,
//output wire [0:0] mem_odt,
//i2c
inout wire i2c_sda,
inout wire i2c_scl,
//spi
input wire spi_miso,
output wire spi_mosi,
output wire spi_sclk,
output wire spi_ssn,
//16550 UART
input wire uart_rx,
output wire uart_tx,
@ -14,20 +39,72 @@ module ghrd_10m50da_top (
//Heart-beat counter
reg [25:0] heart_beat_cnt;
//DDR3 interface assignments
//wire local_init_done;
//wire local_cal_success;
//wire local_cal_fail;
//i2c interface
wire i2c_serial_sda_in ;
wire i2c_serial_scl_in ;
wire i2c_serial_sda_oe ;
wire i2c_serial_scl_oe ;
assign i2c_serial_scl_in = i2c_scl;
assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
assign i2c_serial_sda_in = i2c_sda;
assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
//assign system_resetn = fpga_reset_n & local_init_done;
// SoC sub-system module
ghrd_10m50da ghrd_10m50da_inst (
.clk_clk (clk_50),
.reset_reset_n (fpga_reset_n),
// .ext_flash_flash_dataout_conduit_dataout (qspi_io),
// .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk),
// .ext_flash_flash_ncs_conduit_ncs (qspi_csn),
.clk_clk (clk_50),
//.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
.reset_reset_n (fpga_reset_n),
//.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
.ext_flash_qspi_pins_data (qspi_io),
.ext_flash_qspi_pins_dclk (qspi_clk),
.ext_flash_qspi_pins_ncs (qspi_csn),
//.memory_mem_a (mem_a[12:0] ), // memory.mem_a
//.memory_mem_ba (mem_ba ), // .mem_ba
//.memory_mem_ck (mem_ck ), // .mem_ck
//.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
//.memory_mem_cke (mem_cke ), // .mem_cke
//.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
//.memory_mem_dm (mem_dm ), // .mem_dm
//.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
//.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
//.memory_mem_we_n (mem_we_n ), // .mem_we_n
//.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
//.memory_mem_dq (mem_dq ), // .mem_dq
//.memory_mem_dqs (mem_dqs ), // .mem_dqs
//.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
//.memory_mem_odt (mem_odt ), // .mem_odt
//.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
//.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
//.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
//i2c
.i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
.i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
.i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
.i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
//spi
.spi_0_external_MISO (spi_miso), // spi_0_external.MISO
.spi_0_external_MOSI (spi_mosi), // .MOSI
.spi_0_external_SCLK (spi_sclk), // .SCLK
.spi_0_external_SS_n (spi_ssn), // .SS_n
//pio
.led_external_connection_export (user_led[3:0]),
//16550 UART
.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
);
);
//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
//assign mem_a[13] = 1'b0;
//Heart beat by 50MHz clock
always @(posedge clk_50 or negedge fpga_reset_n)
@ -36,7 +113,7 @@ always @(posedge clk_50 or negedge fpga_reset_n)
else
heart_beat_cnt <= heart_beat_cnt + 1'b1;
assign user_led = {4'hf,heart_beat_cnt[25]};
assign user_led[4] = heart_beat_cnt[25];
endmodule

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@ -10,11 +10,19 @@ set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_
set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
create_clock -name {CLK_50} -period 20.000 {clk_50}
create_clock -name {clk_50} -period 20.000 {clk_50}
set_false_path -to [get_ports {user_led[*]}]
set_false_path -to [get_ports {fpga_reset_n}]
set_false_path -from [get_ports {fpga_reset_n}]
derive_clock_uncertainty
# QSPI interface
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
# UART
set_false_path -from * -to [get_ports {uart_tx}]

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@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Wed Jun 08 19:21:55 MYT 2016
* Generated: Tue Dec 05 14:42:02 SGT 2017
*/
/*
@ -65,12 +65,14 @@
*
*/
#define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108864
#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
#define ONCHIP_MEMORY2_0_REGION_SPAN 167904
#define ONCHIP_MEMORY2_0_REGION_SPAN 131040
#define RESET_REGION_BASE 0x0
#define RESET_REGION_SPAN 32

View file

@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Wed Jun 08 19:18:29 MYT 2016
* Generated: Tue Dec 05 14:41:17 SGT 2017
*/
/*
@ -68,7 +68,7 @@
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x17
#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
@ -91,7 +91,7 @@
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 0x17
#define ALT_CPU_INST_ADDR_WIDTH 0x1c
#define ALT_CPU_NAME "nios2_gen2_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_OCI_VERSION 1
@ -110,7 +110,7 @@
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x17
#define NIOS2_DATA_ADDR_WIDTH 0x1c
#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
@ -132,7 +132,7 @@
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 0x17
#define NIOS2_INST_ADDR_WIDTH 0x1c
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000
@ -144,9 +144,15 @@
*/
#define __ALTERA_16550_UART
#define __ALTERA_AVALON_I2C
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SPI
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER2
#define __ALTERA_MSGDMA
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_ONCHIP_FLASH
@ -193,7 +199,7 @@
*/
#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
#define A_16550_UART_0_BASE 0x440000
#define A_16550_UART_0_BASE 0x100000
#define A_16550_UART_0_FIFO_DEPTH 64
#define A_16550_UART_0_FIFO_MODE 1
#define A_16550_UART_0_FIO_HWFC 0
@ -206,6 +212,46 @@
#define A_16550_UART_0_TYPE "altera_16550_uart"
/*
* ext_flash_avl_csr configuration
*
*/
#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller2
#define EXT_FLASH_AVL_CSR_BASE 0x100240
#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512"
#define EXT_FLASH_AVL_CSR_IRQ 6
#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EXT_FLASH_AVL_CSR_IS_EPCS 0
#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr"
#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024
#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256
#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536
#define EXT_FLASH_AVL_CSR_SPAN 64
#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096
#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller2"
/*
* ext_flash_avl_mem configuration
*
*/
#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller2
#define EXT_FLASH_AVL_MEM_BASE 0x8000000
#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512"
#define EXT_FLASH_AVL_MEM_IRQ -1
#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EXT_FLASH_AVL_MEM_IS_EPCS 0
#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem"
#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024
#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256
#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536
#define EXT_FLASH_AVL_MEM_SPAN 67108864
#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096
#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller2"
/*
* hal configuration
*
@ -217,6 +263,23 @@
#define ALT_TIMESTAMP_CLK none
/*
* i2c_0 configuration
*
*/
#define ALT_MODULE_CLASS_i2c_0 altera_avalon_i2c
#define I2C_0_BASE 0x100200
#define I2C_0_FIFO_DEPTH 16
#define I2C_0_FREQ 50000000
#define I2C_0_IRQ 4
#define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2C_0_NAME "/dev/i2c_0"
#define I2C_0_SPAN 64
#define I2C_0_TYPE "altera_avalon_i2c"
#define I2C_0_USE_AV_ST 0
/*
* jtag_uart_0 configuration
*
@ -235,6 +298,109 @@
#define JTAG_UART_0_WRITE_THRESHOLD 8
/*
* led configuration
*
*/
#define ALT_MODULE_CLASS_led altera_avalon_pio
#define LED_BASE 0x1002e0
#define LED_BIT_CLEARING_EDGE_REGISTER 0
#define LED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_CAPTURE 0
#define LED_DATA_WIDTH 4
#define LED_DO_TEST_BENCH_WIRING 0
#define LED_DRIVEN_SIM_VALUE 0
#define LED_EDGE_TYPE "NONE"
#define LED_FREQ 50000000
#define LED_HAS_IN 0
#define LED_HAS_OUT 1
#define LED_HAS_TRI 0
#define LED_IRQ -1
#define LED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LED_IRQ_TYPE "NONE"
#define LED_NAME "/dev/led"
#define LED_RESET_VALUE 0
#define LED_SPAN 16
#define LED_TYPE "altera_avalon_pio"
/*
* msgdma_0_csr configuration
*
*/
#define ALT_MODULE_CLASS_msgdma_0_csr altera_msgdma
#define MSGDMA_0_CSR_BASE 0x1002c0
#define MSGDMA_0_CSR_BURST_ENABLE 1
#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 1
#define MSGDMA_0_CSR_CHANNEL_ENABLE 0
#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_CHANNEL_WIDTH 8
#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32
#define MSGDMA_0_CSR_DATA_WIDTH 32
#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_CSR_DMA_MODE 0
#define MSGDMA_0_CSR_ENHANCED_FEATURES 0
#define MSGDMA_0_CSR_ERROR_ENABLE 0
#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_ERROR_WIDTH 8
#define MSGDMA_0_CSR_IRQ 3
#define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define MSGDMA_0_CSR_MAX_BURST_COUNT 2
#define MSGDMA_0_CSR_MAX_BYTE 1024
#define MSGDMA_0_CSR_MAX_STRIDE 1
#define MSGDMA_0_CSR_NAME "/dev/msgdma_0_csr"
#define MSGDMA_0_CSR_PACKET_ENABLE 0
#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_CSR_RESPONSE_PORT 2
#define MSGDMA_0_CSR_SPAN 32
#define MSGDMA_0_CSR_STRIDE_ENABLE 0
#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_TRANSFER_TYPE "Aligned Accesses"
#define MSGDMA_0_CSR_TYPE "altera_msgdma"
/*
* msgdma_0_descriptor_slave configuration
*
*/
#define ALT_MODULE_CLASS_msgdma_0_descriptor_slave altera_msgdma
#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ -1
#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_NAME "/dev/msgdma_0_descriptor_slave"
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE "Aligned Accesses"
#define MSGDMA_0_DESCRIPTOR_SLAVE_TYPE "altera_msgdma"
/*
* onchip_flash_0_csr configuration
*
@ -320,12 +486,59 @@
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 167936
#define ONCHIP_MEMORY2_0_SPAN 167936
#define ONCHIP_MEMORY2_0_SIZE_VALUE 131072
#define ONCHIP_MEMORY2_0_SPAN 131072
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1
/*
* spi_0 configuration
*
*/
#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
#define SPI_0_BASE 0x100280
#define SPI_0_CLOCKMULT 1
#define SPI_0_CLOCKPHASE 1
#define SPI_0_CLOCKPOLARITY 0
#define SPI_0_CLOCKUNITS "Hz"
#define SPI_0_DATABITS 8
#define SPI_0_DATAWIDTH 16
#define SPI_0_DELAYMULT "1.0E-9"
#define SPI_0_DELAYUNITS "ns"
#define SPI_0_EXTRADELAY 0
#define SPI_0_INSERT_SYNC 0
#define SPI_0_IRQ 5
#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define SPI_0_ISMASTER 1
#define SPI_0_LSBFIRST 0
#define SPI_0_NAME "/dev/spi_0"
#define SPI_0_NUMSLAVES 1
#define SPI_0_PREFIX "spi_"
#define SPI_0_SPAN 32
#define SPI_0_SYNC_REG_DEPTH 2
#define SPI_0_TARGETCLOCK 128000u
#define SPI_0_TARGETSSDELAY "0.0"
#define SPI_0_TYPE "altera_avalon_spi"
/*
* sysid configuration
*
*/
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
#define SYSID_BASE 0x100300
#define SYSID_ID 0
#define SYSID_IRQ -1
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_NAME "/dev/sysid"
#define SYSID_SPAN 8
#define SYSID_TIMESTAMP 1512455752
#define SYSID_TYPE "altera_avalon_sysid_qsys"
/*
* timer_0 configuration
*
@ -333,7 +546,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x440200
#define TIMER_0_BASE 0x1002a0
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 50000000