diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.dpf b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.dpf
deleted file mode 100644
index 688235e4a0e..00000000000
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.dpf
+++ /dev/null
@@ -1,16 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsf b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsf
index 4c82e5a0cb9..069444ae537 100644
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsf
+++ b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
@@ -52,7 +52,7 @@ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
@@ -74,7 +74,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name SEED 2
+set_global_assignment -name SEED 16
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
@@ -396,4 +396,17 @@ set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v
set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip
set_global_assignment -name SDC_FILE ghrd_timing.sdc
+set_location_assignment PIN_A10 -to i2c_scl
+set_location_assignment PIN_B15 -to i2c_sda
+set_location_assignment PIN_B7 -to spi_sclk
+set_location_assignment PIN_A6 -to spi_miso
+set_location_assignment PIN_C8 -to spi_mosi
+set_location_assignment PIN_C7 -to spi_ssn
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsys b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsys
index 4bee9eff12e..f816798222c 100644
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsys
+++ b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qsys
@@ -26,10 +26,18 @@
}
datum baseAddress
{
- value = "4456448";
+ value = "1048576";
type = "String";
}
}
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
element clk_0
{
datum _sortIndex
@@ -38,6 +46,46 @@
type = "int";
}
}
+ element ext_flash
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element ext_flash.avl_csr
+ {
+ datum baseAddress
+ {
+ value = "1049152";
+ type = "String";
+ }
+ }
+ element ext_flash.avl_mem
+ {
+ datum baseAddress
+ {
+ value = "134217728";
+ type = "String";
+ }
+ }
+ element i2c_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+ element i2c_0.csr
+ {
+ datum baseAddress
+ {
+ value = "1049088";
+ type = "String";
+ }
+ }
element jtag_uart_0
{
datum _sortIndex
@@ -59,6 +107,46 @@
type = "String";
}
}
+ element led
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element led.s1
+ {
+ datum baseAddress
+ {
+ value = "1049312";
+ type = "String";
+ }
+ }
+ element msgdma_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element msgdma_0.csr
+ {
+ datum baseAddress
+ {
+ value = "1049280";
+ type = "String";
+ }
+ }
+ element msgdma_0.descriptor_slave
+ {
+ datum baseAddress
+ {
+ value = "1049328";
+ type = "String";
+ }
+ }
element nios2_gen2_0
{
datum _sortIndex
@@ -135,6 +223,38 @@
type = "String";
}
}
+ element spi_0
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element spi_0.spi_control_port
+ {
+ datum baseAddress
+ {
+ value = "1049216";
+ type = "String";
+ }
+ }
+ element sysid
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element sysid.control_slave
+ {
+ datum baseAddress
+ {
+ value = "1049344";
+ type = "String";
+ }
+ }
element timer_0
{
datum _sortIndex
@@ -152,7 +272,7 @@
}
datum baseAddress
{
- value = "4456960";
+ value = "1049248";
type = "String";
}
}
@@ -188,11 +308,31 @@
type="conduit"
dir="end" />
+
+
+
+
@@ -203,18 +343,204 @@
- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
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+ CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#PORT_LOCKED PORT_UNUSED
+ altpll_avalon_elaboration
+ altpll_avalon_post_edit
+ IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}
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+ IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1
+ MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
+ PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 25.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 25.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1509345238202295.mif PT#ACTIVECLK_CHECK 0
+ UP#locked used UP#c0 used UP#areset used UP#inclk0 used
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+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
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- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
@@ -292,15 +675,15 @@
-
- ]]>
+
+ ]]>
-
+
@@ -327,6 +710,7 @@
+
@@ -414,7 +798,7 @@
@@ -435,7 +819,7 @@
$${FILENAME}_onchip_memory2_0
@@ -444,14 +828,15 @@
- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+
-
+
@@ -463,7 +848,30 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -477,7 +885,7 @@
@@ -486,16 +894,61 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -504,7 +957,7 @@
@@ -513,7 +966,7 @@
@@ -522,7 +975,16 @@
+
+
+
+
+
@@ -531,16 +993,43 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -549,7 +1038,7 @@
@@ -558,7 +1047,7 @@
@@ -566,99 +1055,193 @@
-
-
-
+ kind="avalon"
+ version="17.0"
+ start="msgdma_0.mm_read"
+ end="onchip_memory2_0.s1">
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ version="17.0"
+ start="clk_0.clk_reset"
+ end="i2c_0.reset_sink" />
+
+
+
+ end="msgdma_0.reset_n" />
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qws b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qws
deleted file mode 100644
index 83db95ce95c..00000000000
Binary files a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.qws and /dev/null differ
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sof b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sof
index 54405b2c6cc..6c19755fa6f 100644
Binary files a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sof and b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sof differ
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo
index c3d9cec5885..91d6c0ac929 100644
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo
+++ b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo
@@ -1,11 +1,11 @@
-
-
+
+
java.lang.Integer
- 1467417594
+ 1512455752
false
true
false
@@ -98,7 +98,7 @@
@@ -227,7 +227,7 @@ the requested settings for a module instance. -->
java.lang.String
- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
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@@ -250,7 +250,7 @@ the requested settings for a module instance. -->
true
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@@ -615,7 +615,7 @@ parameters are a RESULT of the module parameters. -->
readdata
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@@ -676,7 +676,7 @@ parameters are a RESULT of the module parameters. -->
clk
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@@ -721,7 +721,7 @@ parameters are a RESULT of the module parameters. -->
reset_n
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@@ -798,7 +798,7 @@ parameters are a RESULT of the module parameters. -->
irq
-
+
@@ -855,7 +855,7 @@ parameters are a RESULT of the module parameters. -->
sout_oe
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+ CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 2 CT#PORT_LOCKED PORT_UNUSED
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 25.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 0 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 25.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 0 PT#STICKY_CLK3 0 PT#STICKY_CLK2 0 PT#STICKY_CLK1 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1509345238202295.mif PT#ACTIVECLK_CHECK 0
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UP#locked used UP#c0 used UP#areset used UP#inclk0 used
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ java.lang.Long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ inclk_interface
+
+
+ java.lang.String
+ MAX 10
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ inclk_interface
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset
+ Input
+ 1
+ reset
+
+
+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 16
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ inclk_interface
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ inclk_interface_reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ read
+ Input
+ 1
+ read
+
+
+ write
+ Input
+ 1
+ write
+
+
+ address
+ Input
+ 2
+ address
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 25000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c0
+ Output
+ 1
+ clk
+
+
+ false
+ ext_flash
+ clock_sink
+ ext_flash.clock_sink
+
+
+
+
@@ -996,7 +2882,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -1061,7 +2947,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -1110,7 +2996,7 @@ parameters are a RESULT of the module parameters. -->
reset_n
-
+
@@ -1178,12 +3064,6 @@ parameters are a RESULT of the module parameters. -->
1
clk
-
- false
- onchip_flash_0
- clk
- onchip_flash_0.clk
-
false
nios2_gen2_0
@@ -1202,6 +3082,30 @@ parameters are a RESULT of the module parameters. -->
clk
timer_0.clk
+
+ false
+ spi_0
+ clk
+ spi_0.clk
+
+
+ false
+ led
+ clk
+ led.clk
+
+
+ false
+ sysid
+ clk
+ sysid.clk
+
+
+ false
+ onchip_flash_0
+ clk
+ onchip_flash_0.clk
+
false
onchip_memory2_0
@@ -1214,8 +3118,26 @@ parameters are a RESULT of the module parameters. -->
clock
a_16550_uart_0.clock
+
+ false
+ msgdma_0
+ clock
+ msgdma_0.clock
+
+
+ false
+ i2c_0
+ clock
+ i2c_0.clock
+
+
+ false
+ altpll_0
+ inclk_interface
+ altpll_0.inclk_interface
+
-
+
@@ -1277,10 +3199,1903 @@ parameters are a RESULT of the module parameters. -->
+
+
+
+ embeddedsw.CMacro.FLASH_TYPE
+ Micron512
+
+
+ embeddedsw.CMacro.IS_EPCS
+ 0
+
+
+ embeddedsw.CMacro.NUMBER_OF_SECTORS
+ 1024
+
+
+ embeddedsw.CMacro.PAGE_SIZE
+ 256
+
+
+ embeddedsw.CMacro.SECTOR_SIZE
+ 65536
+
+
+ embeddedsw.CMacro.SUBSECTOR_SIZE
+ 4096
+
+
+ embeddedsw.dts.compatible
+ altr,quadspi-2.0
+
+
+ embeddedsw.dts.group
+ quadspi
+
+
+ embeddedsw.dts.name
+ quadspi
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ embeddedsw.memoryInfo.GENERATE_DAT_SYM
+ 0
+
+
+ embeddedsw.memoryInfo.GENERATE_FLASH
+ 0
+
+
+ embeddedsw.memoryInfo.GENERATE_HEX
+ 1
+
+
+ embeddedsw.memoryInfo.HEX_INSTALL_DIR
+ QPF_DIR
+
+
+ embeddedsw.memoryInfo.IS_FLASH
+ 1
+
+
+ embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH
+ 32
+
+
+ embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX
+ 1
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ long
+ 25000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clock_sink
+
+
+ int
+ 3
+ true
+ true
+ false
+ true
+
+
+ int
+ 24
+ true
+ true
+ false
+ true
+
+
+ int
+ 4
+ true
+ true
+ false
+ true
+
+
+ int
+ 32
+ true
+ true
+ false
+ true
+
+
+ int
+ 1
+ true
+ true
+ false
+ true
+
+
+ int
+ 1
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ Micron512
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ QUAD
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
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+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ addr
+ Input
+ 4
+ address
+
+
+ read
+ Input
+ 1
+ read
+
+
+ write
+ Input
+ 1
+ write
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ sda_in
+ Input
+ 1
+ sda_in
+
+
+ scl_in
+ Input
+ 1
+ scl_in
+
+
+ sda_oe
+ Output
+ 1
+ sda_oe
+
+
+ scl_oe
+ Output
+ 1
+ scl_oe
+
+
+
@@ -1463,7 +5278,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -1524,7 +5339,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -1569,7 +5384,7 @@ parameters are a RESULT of the module parameters. -->
reset_n
-
+
@@ -1946,7 +5761,7 @@ parameters are a RESULT of the module parameters. -->
waitrequest
-
+
@@ -2024,10 +5839,2781 @@ parameters are a RESULT of the module parameters. -->
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 4
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 0
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 1
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 4
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ Output
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 4
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+ chipselect
+ Input
+ 1
+ chipselect
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ out_port
+ Output
+ 4
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.BURST_ENABLE
+ 1
+
+
+ embeddedsw.CMacro.BURST_WRAPPING_SUPPORT
+ 1
+
+
+ embeddedsw.CMacro.CHANNEL_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.CHANNEL_ENABLE_DERIVED
+ 0
+
+
+ embeddedsw.CMacro.CHANNEL_WIDTH
+ 8
+
+
+ embeddedsw.CMacro.DATA_FIFO_DEPTH
+ 32
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 32
+
+
+ embeddedsw.CMacro.DESCRIPTOR_FIFO_DEPTH
+ 128
+
+
+ embeddedsw.CMacro.DMA_MODE
+ 0
+
+
+ embeddedsw.CMacro.ENHANCED_FEATURES
+ 0
+
+
+ embeddedsw.CMacro.ERROR_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.ERROR_ENABLE_DERIVED
+ 0
+
+
+ embeddedsw.CMacro.ERROR_WIDTH
+ 8
+
+
+ embeddedsw.CMacro.MAX_BURST_COUNT
+ 2
+
+
+ embeddedsw.CMacro.MAX_BYTE
+ 1024
+
+
+ embeddedsw.CMacro.MAX_STRIDE
+ 1
+
+
+ embeddedsw.CMacro.PACKET_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.PACKET_ENABLE_DERIVED
+ 0
+
+
+ embeddedsw.CMacro.PREFETCHER_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.PROGRAMMABLE_BURST_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.RESPONSE_PORT
+ 2
+
+
+ embeddedsw.CMacro.STRIDE_ENABLE
+ 0
+
+
+ embeddedsw.CMacro.STRIDE_ENABLE_DERIVED
+ 0
+
+
+ embeddedsw.CMacro.TRANSFER_TYPE
+ Aligned Accesses
+
+
+ embeddedsw.dts.compatible
+ altr,msgdma-1.0
+
+
+ embeddedsw.dts.group
+ msgdma
+
+
+ embeddedsw.dts.name
+ msgdma
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ true
+ true
+
+
+ int
+ 128
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ int
+ 1024
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ Aligned Accesses
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ true
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ true
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ true
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ true
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ java.lang.String
+ 10M50DAF484C6GES
+ false
+ true
+ false
+ true
+ DEVICE
+
+
+ java.lang.String
+ 6
+ false
+ true
+ false
+ true
+ DEVICE_SPEEDGRADE
+
+
+ com.altera.entityinterfaces.moduleext.AddressMap
+ ]]>
+ false
+ true
+ false
+ true
+ ADDRESS_MAP
+ mm_read
+
+
+ com.altera.entityinterfaces.moduleext.AddressWidthType
+ AddressWidth = 23
+ false
+ true
+ false
+ true
+ ADDRESS_WIDTH
+ mm_read
+
+
+ com.altera.entityinterfaces.moduleext.AddressMap
+ ]]>
+ false
+ true
+ false
+ true
+ ADDRESS_MAP
+ mm_write
+
+
+ com.altera.entityinterfaces.moduleext.AddressWidthType
+ AddressWidth = 23
+ false
+ true
+ false
+ true
+ ADDRESS_WIDTH
+ mm_write
+
+
+ com.altera.entityinterfaces.moduleext.AddressMap
+
+ false
+ true
+ false
+ true
+ ADDRESS_MAP
+ descriptor_read_master
+
+
+ com.altera.entityinterfaces.moduleext.AddressWidthType
+ AddressWidth = -1
+ false
+ true
+ false
+ true
+ ADDRESS_WIDTH
+ descriptor_read_master
+
+
+ com.altera.entityinterfaces.moduleext.AddressMap
+
+ false
+ true
+ false
+ true
+ ADDRESS_MAP
+ descriptor_write_master
+
+
+ com.altera.entityinterfaces.moduleext.AddressWidthType
+ AddressWidth = -1
+ false
+ true
+ false
+ true
+ ADDRESS_WIDTH
+ descriptor_write_master
+
+
+ java.lang.String
+ MAX 10
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ SYMBOLS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset_n
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ true
+
+ mm_read_address
+ Output
+ 23
+ address
+
+
+ mm_read_read
+ Output
+ 1
+ read
+
+
+ mm_read_byteenable
+ Output
+ 4
+ byteenable
+
+
+ mm_read_readdata
+ Input
+ 32
+ readdata
+
+
+ mm_read_waitrequest
+ Input
+ 1
+ waitrequest
+
+
+ mm_read_readdatavalid
+ Input
+ 1
+ readdatavalid
+
+
+ mm_read_burstcount
+ Output
+ 2
+ burstcount
+
+
+ false
+ onchip_memory2_0
+ s1
+ onchip_memory2_0.s1
+ 4194304
+ 131072
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ SYMBOLS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset_n
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ true
+
+ mm_write_address
+ Output
+ 23
+ address
+
+
+ mm_write_write
+ Output
+ 1
+ write
+
+
+ mm_write_byteenable
+ Output
+ 4
+ byteenable
+
+
+ mm_write_writedata
+ Output
+ 32
+ writedata
+
+
+ mm_write_waitrequest
+ Input
+ 1
+ waitrequest
+
+
+ mm_write_burstcount
+ Output
+ 2
+ burstcount
+
+
+ false
+ onchip_memory2_0
+ s1
+ onchip_memory2_0.s1
+ 4194304
+ 131072
+
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clock_clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n_reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 32
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset_n
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ csr_writedata
+ Input
+ 32
+ writedata
+
+
+ csr_write
+ Input
+ 1
+ write
+
+
+ csr_byteenable
+ Input
+ 4
+ byteenable
+
+
+ csr_readdata
+ Output
+ 32
+ readdata
+
+
+ csr_read
+ Input
+ 1
+ read
+
+
+ csr_address
+ Input
+ 3
+ address
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 16
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset_n
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ descriptor_slave_write
+ Input
+ 1
+ write
+
+
+ descriptor_slave_waitrequest
+ Output
+ 1
+ waitrequest
+
+
+ descriptor_slave_writedata
+ Input
+ 128
+ writedata
+
+
+ descriptor_slave_byteenable
+ Input
+ 16
+ byteenable
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ msgdma_0.csr
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset_n
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ csr_irq_irq
+ Output
+ 1
+ irq
+
+
+
@@ -2065,7 +8651,7 @@ the requested settings for a module instance. -->
embeddedsw.CMacro.DATA_ADDR_WIDTH
- 23
+ 28
embeddedsw.CMacro.DCACHE_BYPASS_MASK
@@ -2153,7 +8739,7 @@ the requested settings for a module instance. -->
embeddedsw.CMacro.INST_ADDR_WIDTH
- 23
+ 28
embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS
@@ -2351,6 +8937,14 @@ the requested settings for a module instance. -->
false
true
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
boolean
false
@@ -3513,7 +10107,7 @@ the requested settings for a module instance. -->
int
- 23
+ 28
false
true
false
@@ -3533,7 +10127,7 @@ the requested settings for a module instance. -->
int
- 23
+ 28
false
true
false
@@ -3643,7 +10237,7 @@ the requested settings for a module instance. -->
java.lang.String
- ]]>
+ ]]>
false
true
false
@@ -3663,7 +10257,7 @@ the requested settings for a module instance. -->
java.lang.String
- ]]>
+ ]]>
false
true
false
@@ -3792,7 +10386,7 @@ the requested settings for a module instance. -->
long
- 7
+ 127
false
true
false
@@ -3842,7 +10436,7 @@ the requested settings for a module instance. -->
java.lang.String
- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
false
true
false
@@ -3869,7 +10463,7 @@ the requested settings for a module instance. -->
java.lang.Integer
- 1
+ 2
false
true
false
@@ -3879,7 +10473,7 @@ the requested settings for a module instance. -->
java.lang.Integer
- 1
+ 2
false
true
false
@@ -3903,7 +10497,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -3964,7 +10558,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -4015,7 +10609,7 @@ parameters are a RESULT of the module parameters. -->
reset_req
-
+
@@ -4284,7 +10878,7 @@ parameters are a RESULT of the module parameters. -->
d_address
Output
- 23
+ 28
address
@@ -4348,9 +10942,49 @@ parameters are a RESULT of the module parameters. -->
a_16550_uart_0
avalon_slave
a_16550_uart_0.avalon_slave
- 4456448
+ 1048576
512
+
+ false
+ ext_flash
+ avl_csr
+ ext_flash.avl_csr
+ 1049152
+ 64
+
+
+ false
+ ext_flash
+ avl_mem
+ ext_flash.avl_mem
+ 134217728
+ 67108864
+
+
+ false
+ sysid
+ control_slave
+ sysid.control_slave
+ 1049344
+ 8
+
+
+ false
+ msgdma_0
+ csr
+ msgdma_0.csr
+ 1049280
+ 32
+
+
+ false
+ i2c_0
+ csr
+ i2c_0.csr
+ 1049088
+ 64
+
false
onchip_flash_0
@@ -4375,24 +11009,48 @@ parameters are a RESULT of the module parameters. -->
2099200
2048
+
+ false
+ msgdma_0
+ descriptor_slave
+ msgdma_0.descriptor_slave
+ 1049328
+ 16
+
false
onchip_memory2_0
s1
onchip_memory2_0.s1
4194304
- 167936
+ 131072
false
timer_0
s1
timer_0.s1
- 4456960
+ 1049248
+ 32
+
+
+ false
+ led
+ s1
+ led.s1
+ 1049312
+ 16
+
+
+ false
+ spi_0
+ spi_control_port
+ spi_0.spi_control_port
+ 1049216
32
-
+
@@ -4657,7 +11315,7 @@ parameters are a RESULT of the module parameters. -->
i_address
Output
- 23
+ 28
address
@@ -4684,6 +11342,14 @@ parameters are a RESULT of the module parameters. -->
1
readdatavalid
+
+ false
+ ext_flash
+ avl_mem
+ ext_flash.avl_mem
+ 134217728
+ 67108864
+
false
onchip_flash_0
@@ -4706,10 +11372,10 @@ parameters are a RESULT of the module parameters. -->
s1
onchip_memory2_0.s1
4194304
- 167936
+ 131072
-
+
@@ -4777,6 +11443,27 @@ parameters are a RESULT of the module parameters. -->
32
irq
+
+ false
+ msgdma_0
+ csr_irq
+ msgdma_0.csr_irq
+ 3
+
+
+ false
+ i2c_0
+ interrupt_sender
+ i2c_0.interrupt_sender
+ 4
+
+
+ false
+ ext_flash
+ interrupt_sender
+ ext_flash.interrupt_sender
+ 6
+
false
jtag_uart_0
@@ -4791,6 +11478,13 @@ parameters are a RESULT of the module parameters. -->
timer_0.irq
2
+
+ false
+ spi_0
+ irq
+ spi_0.irq
+ 5
+
false
a_16550_uart_0
@@ -4799,7 +11493,7 @@ parameters are a RESULT of the module parameters. -->
1
-
+
@@ -4860,7 +11554,7 @@ parameters are a RESULT of the module parameters. -->
reset
-
+
@@ -5238,7 +11932,7 @@ parameters are a RESULT of the module parameters. -->
+ version="17.0">
@@ -5327,7 +12021,7 @@ parameters are a RESULT of the module parameters. -->
@@ -5948,7 +12642,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -6009,7 +12703,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -6054,7 +12748,7 @@ parameters are a RESULT of the module parameters. -->
reset_n
-
+
@@ -6437,7 +13131,7 @@ parameters are a RESULT of the module parameters. -->
burstcount
-
+
@@ -6806,7 +13500,7 @@ parameters are a RESULT of the module parameters. -->
@@ -6864,7 +13558,7 @@ the requested settings for a module instance. -->
embeddedsw.CMacro.SIZE_VALUE
- 167936
+ 131072
embeddedsw.CMacro.WRITABLE
@@ -6954,6 +13648,14 @@ the requested settings for a module instance. -->
true
true
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
boolean
false
@@ -6970,6 +13672,14 @@ the requested settings for a module instance. -->
true
true
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
java.lang.String
NONE
@@ -6980,7 +13690,7 @@ the requested settings for a module instance. -->
long
- 167936
+ 131072
false
true
true
@@ -7018,6 +13728,14 @@ the requested settings for a module instance. -->
true
true
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
int
1
@@ -7102,7 +13820,7 @@ the requested settings for a module instance. -->
java.lang.String
- ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
false
true
false
@@ -7111,7 +13829,7 @@ the requested settings for a module instance. -->
int
- 16
+ 15
true
true
false
@@ -7119,7 +13837,7 @@ the requested settings for a module instance. -->
int
- 16
+ 15
true
true
false
@@ -7173,7 +13891,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -7218,7 +13936,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -7256,7 +13974,7 @@ parameters are a RESULT of the module parameters. -->
java.math.BigInteger
- 167936
+ 131072
true
true
false
@@ -7344,7 +14062,7 @@ parameters are a RESULT of the module parameters. -->
java.math.BigInteger
- 167936
+ 131072
false
true
true
@@ -7555,7 +14273,7 @@ parameters are a RESULT of the module parameters. -->
address
Input
- 16
+ 15
address
@@ -7595,7 +14313,7 @@ parameters are a RESULT of the module parameters. -->
byteenable
-
+
@@ -7647,10 +14365,1384 @@ parameters are a RESULT of the module parameters. -->
+
+
+
+ embeddedsw.CMacro.CLOCKMULT
+ 1
+
+
+ embeddedsw.CMacro.CLOCKPHASE
+ 1
+
+
+ embeddedsw.CMacro.CLOCKPOLARITY
+ 0
+
+
+ embeddedsw.CMacro.CLOCKUNITS
+ "Hz"
+
+
+ embeddedsw.CMacro.DATABITS
+ 8
+
+
+ embeddedsw.CMacro.DATAWIDTH
+ 16
+
+
+ embeddedsw.CMacro.DELAYMULT
+ "1.0E-9"
+
+
+ embeddedsw.CMacro.DELAYUNITS
+ "ns"
+
+
+ embeddedsw.CMacro.EXTRADELAY
+ 0
+
+
+ embeddedsw.CMacro.INSERT_SYNC
+ 0
+
+
+ embeddedsw.CMacro.ISMASTER
+ 1
+
+
+ embeddedsw.CMacro.LSBFIRST
+ 0
+
+
+ embeddedsw.CMacro.NUMSLAVES
+ 1
+
+
+ embeddedsw.CMacro.PREFIX
+ "spi_"
+
+
+ embeddedsw.CMacro.SYNC_REG_DEPTH
+ 2
+
+
+ embeddedsw.CMacro.TARGETCLOCK
+ 128000u
+
+
+ embeddedsw.CMacro.TARGETSSDELAY
+ "0.0"
+
+
+ embeddedsw.dts.compatible
+ altr,spi-1.0
+
+
+ embeddedsw.dts.group
+ spi
+
+
+ embeddedsw.dts.name
+ spi
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ false
+ true
+ true
+
+
+ long
+ 128000
+ false
+ true
+ true
+ true
+
+
+ double
+ 0.0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ 2.0
+ false
+ true
+ false
+ true
+ AVALON_SPEC
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ double
+ 127551.0
+ true
+ true
+ true
+ true
+
+
+ double
+ 0.0
+ true
+ false
+ true
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ int
+ 16
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ data_from_cpu
+ Input
+ 16
+ writedata
+
+
+ data_to_cpu
+ Output
+ 16
+ readdata
+
+
+ mem_addr
+ Input
+ 3
+ address
+
+
+ read_n
+ Input
+ 1
+ read_n
+
+
+ spi_select
+ Input
+ 1
+ chipselect
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ spi_0.spi_control_port
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ irq
+ Output
+ 1
+ irq
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ MISO
+ Input
+ 1
+ export
+
+
+ MOSI
+ Output
+ 1
+ export
+
+
+ SCLK
+ Output
+ 1
+ export
+
+
+ SS_n
+ Output
+ 1
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.ID
+ 0
+
+
+ embeddedsw.CMacro.TIMESTAMP
+ 1512455752
+
+
+ embeddedsw.dts.compatible
+ altr,sysid-1.0
+
+
+ embeddedsw.dts.group
+ sysid
+
+
+ embeddedsw.dts.name
+ sysid
+
+
+ embeddedsw.dts.params.id
+ 0
+
+
+ embeddedsw.dts.params.timestamp
+ 1512455752
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1512455752
+ true
+ false
+ false
+ true
+ GENERATION_ID
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clock
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+ address
+ Input
+ 1
+ address
+
+
+
@@ -7876,7 +15968,7 @@ the requested settings for a module instance. -->
true
true
-
+
@@ -7937,7 +16029,7 @@ parameters are a RESULT of the module parameters. -->
clk
-
+
@@ -7982,7 +16074,7 @@ parameters are a RESULT of the module parameters. -->
reset_n
-
+
@@ -8351,7 +16443,7 @@ parameters are a RESULT of the module parameters. -->
write_n
-
+
@@ -8432,7 +16524,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8483,7 +16575,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8496,7 +16588,7 @@ parameters are a RESULT of the module parameters. -->
java.math.BigInteger
- 0x00440000
+ 0x00100000
false
true
true
@@ -8531,10 +16623,265 @@ parameters are a RESULT of the module parameters. -->
a_16550_uart_0
avalon_slave
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00100240
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ ext_flash
+ avl_csr
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x08000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ ext_flash
+ avl_mem
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00100300
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ sysid
+ control_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x001002c0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ msgdma_0
+ csr
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00100200
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ i2c_0
+ csr
+
@@ -8585,7 +16932,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8636,7 +16983,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8684,10 +17031,61 @@ parameters are a RESULT of the module parameters. -->
nios2_gen2_0
debug_mem_slave
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x001002f0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ msgdma_0
+ descriptor_slave
+
@@ -8738,7 +17136,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8751,7 +17149,7 @@ parameters are a RESULT of the module parameters. -->
java.math.BigInteger
- 0x00440200
+ 0x001002a0
false
true
true
@@ -8786,10 +17184,163 @@ parameters are a RESULT of the module parameters. -->
timer_0
s1
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x001002e0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ led
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00100280
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ data_master
+ spi_0
+ spi_control_port
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x08000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ instruction_master
+ ext_flash
+ avl_mem
+
@@ -8840,7 +17391,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8891,7 +17442,7 @@ parameters are a RESULT of the module parameters. -->
@@ -8940,11 +17491,35 @@ parameters are a RESULT of the module parameters. -->
s1
+ name="msgdma_0.mm_read/onchip_memory2_0.s1"
+ kind="avalon"
+ version="17.0"
+ start="msgdma_0.mm_read"
+ end="onchip_memory2_0.s1">
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00400000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
java.lang.String
UNKNOWN
@@ -8961,15 +17536,93 @@ parameters are a RESULT of the module parameters. -->
true
true
- clk_0
- clk
- onchip_flash_0
- clk
+ msgdma_0
+ mm_read
+ onchip_memory2_0
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00400000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ msgdma_0
+ mm_write
+ onchip_memory2_0
+ s1
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c0
+ ext_flash
+ clock_sink
@@ -8996,7 +17649,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9023,7 +17676,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9047,10 +17700,118 @@ parameters are a RESULT of the module parameters. -->
timer_0
clk
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ spi_0
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ led
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ sysid
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ onchip_flash_0
+ clk
+
@@ -9077,7 +17838,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9101,10 +17862,196 @@ parameters are a RESULT of the module parameters. -->
a_16550_uart_0
clock
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ msgdma_0
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ i2c_0
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk
+ altpll_0
+ inclk_interface
+
+
+
+ int
+ 3
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ irq
+ msgdma_0
+ csr_irq
+
+
+
+ int
+ 4
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ irq
+ i2c_0
+ interrupt_sender
+
+
+
+ int
+ 6
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ irq
+ ext_flash
+ interrupt_sender
+
@@ -9139,7 +18086,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9171,10 +18118,45 @@ parameters are a RESULT of the module parameters. -->
timer_0
irq
+
+
+ int
+ 5
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ irq
+ spi_0
+ irq
+
@@ -9206,10 +18188,37 @@ parameters are a RESULT of the module parameters. -->
a_16550_uart_0
irq_sender
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ altpll_0
+ inclk_interface_reset
+
@@ -9236,7 +18245,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9263,7 +18272,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9290,7 +18299,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9314,10 +18323,118 @@ parameters are a RESULT of the module parameters. -->
timer_0
reset
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ spi_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ ext_flash
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ led
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ sysid
+ reset
+
@@ -9341,10 +18458,37 @@ parameters are a RESULT of the module parameters. -->
onchip_memory2_0
reset1
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_0
+ clk_reset
+ msgdma_0
+ reset_n
+
@@ -9369,11 +18513,11 @@ parameters are a RESULT of the module parameters. -->
reset_sink
+ version="17.0"
+ start="clk_0.clk_reset"
+ end="i2c_0.reset_sink">
java.lang.String
UNKNOWN
@@ -9390,15 +18534,15 @@ parameters are a RESULT of the module parameters. -->
true
true
- nios2_gen2_0
- debug_reset_request
- onchip_flash_0
- nreset
+ clk_0
+ clk_reset
+ i2c_0
+ reset_sink
@@ -9425,7 +18569,7 @@ parameters are a RESULT of the module parameters. -->
@@ -9449,10 +18593,91 @@ parameters are a RESULT of the module parameters. -->
jtag_uart_0
reset
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ debug_reset_request
+ spi_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ debug_reset_request
+ ext_flash
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2_0
+ debug_reset_request
+ led
+ reset
+
@@ -9477,11 +18702,11 @@ parameters are a RESULT of the module parameters. -->
reset1
+ end="msgdma_0.reset_n">
java.lang.String
UNKNOWN
@@ -9500,8 +18725,8 @@ parameters are a RESULT of the module parameters. -->
nios2_gen2_0
debug_reset_request
- a_16550_uart_0
- reset_sink
+ msgdma_0
+ reset_n
1
@@ -9509,71 +18734,55 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
Altera 16550 Compatible UART
- 16.0
+ 17.0
- 7
+ 16
avalon_slave
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Avalon Memory Mapped Slave
- 16.0
+ 17.0
- 6
+ 13
clock_sink
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Clock Input
- 16.0
+ 17.0
- 6
+ 13
reset_sink
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Reset Input
- 16.0
+ 17.0
- 3
+ 7
interrupt_sender
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Interrupt Sender
- 16.0
+ 17.0
- 2
+ 6
conduit_end
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Conduit
- 16.0
+ 17.0
1
- clock_source
+ altpll
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
- Clock Source
- 16.0
-
-
- 1
- clock_sink
- com.altera.entityinterfaces.IElementClass
- com.altera.entityinterfaces.IMutableConnectionPoint
- Clock Input
- 16.0
-
-
- 1
- reset_sink
- com.altera.entityinterfaces.IElementClass
- com.altera.entityinterfaces.IMutableConnectionPoint
- Reset Input
- 16.0
+ Avalon ALTPLL
+ 17.0
1
@@ -9581,7 +18790,39 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Clock Output
- 16.0
+ 17.0
+
+
+ 1
+ clock_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Clock Source
+ 17.0
+
+
+ 1
+ clock_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Input
+ 17.0
+
+
+ 1
+ reset_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Reset Input
+ 17.0
+
+
+ 1
+ clock_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Output
+ 17.0
1
@@ -9589,7 +18830,23 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Reset Output
- 16.0
+ 17.0
+
+
+ 1
+ altera_generic_quad_spi_controller2
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Altera Generic QUAD SPI controller II
+ 17.0
+
+
+ 1
+ altera_avalon_i2c
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Altera Avalon I2C (Master)
+ 17.0
1
@@ -9597,7 +18854,31 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
JTAG UART
- 16.0
+ 17.0
+
+
+ 1
+ altera_avalon_pio
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ PIO (Parallel I/O)
+ 17.0
+
+
+ 1
+ altera_msgdma
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Modular Scatter-Gather DMA
+ 17.0
+
+
+ 4
+ avalon_master
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Avalon Memory Mapped Master
+ 17.0
1
@@ -9605,15 +18886,7 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
Nios II Processor
- 16.0
-
-
- 2
- avalon_master
- com.altera.entityinterfaces.IElementClass
- com.altera.entityinterfaces.IMutableConnectionPoint
- Avalon Memory Mapped Master
- 16.0
+ 17.0
1
@@ -9621,7 +18894,7 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Interrupt Receiver
- 16.0
+ 17.0
1
@@ -9629,7 +18902,7 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Reset Output
- 16.0
+ 17.0
1
@@ -9637,7 +18910,7 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IMutableConnectionPoint
Custom Instruction Master
- 16.0
+ 17.0
1
@@ -9645,7 +18918,7 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
Altera On-Chip Flash
- 16.0
+ 17.0
1
@@ -9653,7 +18926,23 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
On-Chip Memory (RAM or ROM)
- 16.0
+ 17.0
+
+
+ 1
+ altera_avalon_spi
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ SPI (3 Wire Serial)
+ 17.0
+
+
+ 1
+ altera_avalon_sysid_qsys
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ System ID Peripheral
+ 17.0
1
@@ -9661,40 +18950,40 @@ parameters are a RESULT of the module parameters. -->
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IModule
Interval Timer
- 16.0
+ 17.0
- 10
+ 21
avalon
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IConnection
Avalon Memory Mapped Connection
- 16.0
+ 17.0
- 6
+ 13
clock
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IConnection
Clock Connection
- 16.0
+ 17.0
- 3
+ 7
interrupt
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IConnection
Interrupt Connection
- 16.0
+ 17.0
- 11
+ 20
reset
com.altera.entityinterfaces.IElementClass
com.altera.entityinterfaces.IConnection
Reset Connection
- 16.0
+ 17.0
- 16.0 211
+ 17.0 595
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da_top.v b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da_top.v
index 5147a9a6f25..846659543a4 100644
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da_top.v
+++ b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_10m50da_top.v
@@ -1,11 +1,36 @@
module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
+ //input wire clk_ddr3_100_p,
input wire fpga_reset_n,
//QSPI
-// output wire qspi_clk,
-// inout wire[3:0] qspi_io,
-// output wire qspi_csn,
+ output wire qspi_clk,
+ inout wire[3:0] qspi_io,
+ output wire qspi_csn,
+ //ddr3
+ //output wire [13:0] mem_a,
+ //output wire [2:0] mem_ba,
+ //inout wire [0:0] mem_ck,
+ //inout wire [0:0] mem_ck_n,
+ //output wire [0:0] mem_cke,
+ //output wire [0:0] mem_cs_n,
+ //output wire [0:0] mem_dm,
+ //output wire [0:0] mem_ras_n,
+ //output wire [0:0] mem_cas_n,
+ //output wire [0:0] mem_we_n,
+ //output wire mem_reset_n,
+ ///inout wire [7:0] mem_dq,
+ //inout wire [0:0] mem_dqs,
+ //inout wire [0:0] mem_dqs_n,
+ //output wire [0:0] mem_odt,
+ //i2c
+ inout wire i2c_sda,
+ inout wire i2c_scl,
+ //spi
+ input wire spi_miso,
+ output wire spi_mosi,
+ output wire spi_sclk,
+ output wire spi_ssn,
//16550 UART
input wire uart_rx,
output wire uart_tx,
@@ -14,20 +39,72 @@ module ghrd_10m50da_top (
//Heart-beat counter
reg [25:0] heart_beat_cnt;
+//DDR3 interface assignments
+//wire local_init_done;
+//wire local_cal_success;
+//wire local_cal_fail;
+
+//i2c interface
+wire i2c_serial_sda_in ;
+wire i2c_serial_scl_in ;
+wire i2c_serial_sda_oe ;
+wire i2c_serial_scl_oe ;
+assign i2c_serial_scl_in = i2c_scl;
+assign i2c_scl = i2c_serial_scl_oe ? 1'b0 : 1'bz;
+
+assign i2c_serial_sda_in = i2c_sda;
+assign i2c_sda = i2c_serial_sda_oe ? 1'b0 : 1'bz;
+
+//assign system_resetn = fpga_reset_n & local_init_done;
+
// SoC sub-system module
ghrd_10m50da ghrd_10m50da_inst (
- .clk_clk (clk_50),
- .reset_reset_n (fpga_reset_n),
-// .ext_flash_flash_dataout_conduit_dataout (qspi_io),
-// .ext_flash_flash_dclk_out_conduit_dclk_out (qspi_clk),
-// .ext_flash_flash_ncs_conduit_ncs (qspi_csn),
+ .clk_clk (clk_50),
+ //.ref_clock_bridge_in_clk_clk (clk_ddr3_100_p),
+ .reset_reset_n (fpga_reset_n),
+ //.mem_resetn_in_reset_reset_n (fpga_reset_n ), // mem_resetn_in_reset.reset_n
+ .ext_flash_qspi_pins_data (qspi_io),
+ .ext_flash_qspi_pins_dclk (qspi_clk),
+ .ext_flash_qspi_pins_ncs (qspi_csn),
+ //.memory_mem_a (mem_a[12:0] ), // memory.mem_a
+ //.memory_mem_ba (mem_ba ), // .mem_ba
+ //.memory_mem_ck (mem_ck ), // .mem_ck
+ //.memory_mem_ck_n (mem_ck_n ), // .mem_ck_n
+ //.memory_mem_cke (mem_cke ), // .mem_cke
+ //.memory_mem_cs_n (mem_cs_n ), // .mem_cs_n
+ //.memory_mem_dm (mem_dm ), // .mem_dm
+ //.memory_mem_ras_n (mem_ras_n ), // .mem_ras_n
+ //.memory_mem_cas_n (mem_cas_n ), // .mem_cas_n
+ //.memory_mem_we_n (mem_we_n ), // .mem_we_n
+ //.memory_mem_reset_n (mem_reset_n ), // .mem_reset_n
+ //.memory_mem_dq (mem_dq ), // .mem_dq
+ //.memory_mem_dqs (mem_dqs ), // .mem_dqs
+ //.memory_mem_dqs_n (mem_dqs_n ), // .mem_dqs_n
+ //.memory_mem_odt (mem_odt ), // .mem_odt
+ //.mem_if_ddr3_emif_0_status_local_init_done (local_init_done ), // mem_if_ddr3_emif_0_status.local_init_done
+ //.mem_if_ddr3_emif_0_status_local_cal_success (local_cal_success ), // .local_cal_success
+ //.mem_if_ddr3_emif_0_status_local_cal_fail (local_cal_fail ), // .local_cal_fail
+ //i2c
+ .i2c_0_i2c_serial_sda_in (i2c_serial_sda_in),
+ .i2c_0_i2c_serial_scl_in (i2c_serial_scl_in),
+ .i2c_0_i2c_serial_sda_oe (i2c_serial_sda_oe),
+ .i2c_0_i2c_serial_scl_oe (i2c_serial_scl_oe),
+ //spi
+ .spi_0_external_MISO (spi_miso), // spi_0_external.MISO
+ .spi_0_external_MOSI (spi_mosi), // .MOSI
+ .spi_0_external_SCLK (spi_sclk), // .SCLK
+ .spi_0_external_SS_n (spi_ssn), // .SS_n
+ //pio
+ .led_external_connection_export (user_led[3:0]),
//16550 UART
.a_16550_uart_0_rs_232_serial_sin (uart_rx), // a_16550_uart_0_rs_232_serial.sin
.a_16550_uart_0_rs_232_serial_sout (uart_tx), // .sout
.a_16550_uart_0_rs_232_serial_sout_oe () // .sout_oe
-);
+);
+//DDR3 Address Bit #13 is not available for DDR3 SDRAM A (64Mx16)
+//assign mem_a[13] = 1'b0;
//Heart beat by 50MHz clock
always @(posedge clk_50 or negedge fpga_reset_n)
@@ -36,7 +113,7 @@ always @(posedge clk_50 or negedge fpga_reset_n)
else
heart_beat_cnt <= heart_beat_cnt + 1'b1;
-assign user_led = {4'hf,heart_beat_cnt[25]};
+assign user_led[4] = heart_beat_cnt[25];
endmodule
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_timing.sdc b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_timing.sdc
index d44f39d0146..5f962e7c58e 100644
--- a/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_timing.sdc
+++ b/arch/nios2/soc/nios2f-zephyr/cpu/ghrd_timing.sdc
@@ -10,11 +10,19 @@ set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_
set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms]
set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo]
-create_clock -name {CLK_50} -period 20.000 {clk_50}
+create_clock -name {clk_50} -period 20.000 {clk_50}
set_false_path -to [get_ports {user_led[*]}]
set_false_path -to [get_ports {fpga_reset_n}]
set_false_path -from [get_ports {fpga_reset_n}]
+derive_clock_uncertainty
+
+# QSPI interface
+set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_io[*]}]
+set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_clk}]
+set_output_delay -clock {clk_50 } -rise -min 11 [get_ports {qspi_csn}]
+set_input_delay -clock {clk_50 } -rise -min 10 [get_ports {qspi_io[*]}]
+
# UART
set_false_path -from * -to [get_ports {uart_tx}]
diff --git a/arch/nios2/soc/nios2f-zephyr/cpu/stp1.stp b/arch/nios2/soc/nios2f-zephyr/cpu/stp1.stp
deleted file mode 100644
index 38403b9b967..00000000000
--- a/arch/nios2/soc/nios2f-zephyr/cpu/stp1.stp
+++ /dev/null
@@ -1,1045 +0,0 @@
-
-
-
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- 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[0]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[10]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[11]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[12]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[13]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[14]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[15]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[16]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[17]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[18]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[19]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[1]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[20]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[21]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[22]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[2]' == high && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[3]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[4]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[5]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[6]' == high && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[7]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[8]' == low && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_address[9]' == high && 'ghrd_10m50da:ghrd_10m50da_inst|ghrd_10m50da_nios2_gen2_0:nios2_gen2_0|i_read' == rising edge
-
-
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-
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-
- 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
- 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
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diff --git a/arch/nios2/soc/nios2f-zephyr/include/linker.h b/arch/nios2/soc/nios2f-zephyr/include/linker.h
index 164bf8873d3..3a3c5617945 100644
--- a/arch/nios2/soc/nios2f-zephyr/include/linker.h
+++ b/arch/nios2/soc/nios2f-zephyr/include/linker.h
@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
- * Generated: Wed Jun 08 19:21:55 MYT 2016
+ * Generated: Tue Dec 05 14:42:02 SGT 2017
*/
/*
@@ -65,12 +65,14 @@
*
*/
+#define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
+#define EXT_FLASH_AVL_MEM_REGION_SPAN 67108864
#define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
#define ONCHIP_FLASH_0_DATA_REGION_SPAN 753632
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
#define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_SPAN 32
#define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
-#define ONCHIP_MEMORY2_0_REGION_SPAN 167904
+#define ONCHIP_MEMORY2_0_REGION_SPAN 131040
#define RESET_REGION_BASE 0x0
#define RESET_REGION_SPAN 32
diff --git a/arch/nios2/soc/nios2f-zephyr/include/system.h b/arch/nios2/soc/nios2f-zephyr/include/system.h
index 8fcd98a3b0d..02f83fcf0fb 100644
--- a/arch/nios2/soc/nios2f-zephyr/include/system.h
+++ b/arch/nios2/soc/nios2f-zephyr/include/system.h
@@ -4,7 +4,7 @@
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
- * Generated: Wed Jun 08 19:18:29 MYT 2016
+ * Generated: Tue Dec 05 14:41:17 SGT 2017
*/
/*
@@ -68,7 +68,7 @@
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
-#define ALT_CPU_DATA_ADDR_WIDTH 0x17
+#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
#define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
@@ -91,7 +91,7 @@
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INITDA_SUPPORTED
-#define ALT_CPU_INST_ADDR_WIDTH 0x17
+#define ALT_CPU_INST_ADDR_WIDTH 0x1c
#define ALT_CPU_NAME "nios2_gen2_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_OCI_VERSION 1
@@ -110,7 +110,7 @@
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
-#define NIOS2_DATA_ADDR_WIDTH 0x17
+#define NIOS2_DATA_ADDR_WIDTH 0x1c
#define NIOS2_DCACHE_BYPASS_MASK 0x80000000
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
@@ -132,7 +132,7 @@
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INITDA_SUPPORTED
-#define NIOS2_INST_ADDR_WIDTH 0x17
+#define NIOS2_INST_ADDR_WIDTH 0x1c
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000
@@ -144,9 +144,15 @@
*/
#define __ALTERA_16550_UART
+#define __ALTERA_AVALON_I2C
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
+#define __ALTERA_AVALON_PIO
+#define __ALTERA_AVALON_SPI
+#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
+#define __ALTERA_GENERIC_QUAD_SPI_CONTROLLER2
+#define __ALTERA_MSGDMA
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_ONCHIP_FLASH
@@ -193,7 +199,7 @@
*/
#define ALT_MODULE_CLASS_a_16550_uart_0 altera_16550_uart
-#define A_16550_UART_0_BASE 0x440000
+#define A_16550_UART_0_BASE 0x100000
#define A_16550_UART_0_FIFO_DEPTH 64
#define A_16550_UART_0_FIFO_MODE 1
#define A_16550_UART_0_FIO_HWFC 0
@@ -206,6 +212,46 @@
#define A_16550_UART_0_TYPE "altera_16550_uart"
+/*
+ * ext_flash_avl_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_ext_flash_avl_csr altera_generic_quad_spi_controller2
+#define EXT_FLASH_AVL_CSR_BASE 0x100240
+#define EXT_FLASH_AVL_CSR_FLASH_TYPE "Micron512"
+#define EXT_FLASH_AVL_CSR_IRQ 6
+#define EXT_FLASH_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define EXT_FLASH_AVL_CSR_IS_EPCS 0
+#define EXT_FLASH_AVL_CSR_NAME "/dev/ext_flash_avl_csr"
+#define EXT_FLASH_AVL_CSR_NUMBER_OF_SECTORS 1024
+#define EXT_FLASH_AVL_CSR_PAGE_SIZE 256
+#define EXT_FLASH_AVL_CSR_SECTOR_SIZE 65536
+#define EXT_FLASH_AVL_CSR_SPAN 64
+#define EXT_FLASH_AVL_CSR_SUBSECTOR_SIZE 4096
+#define EXT_FLASH_AVL_CSR_TYPE "altera_generic_quad_spi_controller2"
+
+
+/*
+ * ext_flash_avl_mem configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_ext_flash_avl_mem altera_generic_quad_spi_controller2
+#define EXT_FLASH_AVL_MEM_BASE 0x8000000
+#define EXT_FLASH_AVL_MEM_FLASH_TYPE "Micron512"
+#define EXT_FLASH_AVL_MEM_IRQ -1
+#define EXT_FLASH_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define EXT_FLASH_AVL_MEM_IS_EPCS 0
+#define EXT_FLASH_AVL_MEM_NAME "/dev/ext_flash_avl_mem"
+#define EXT_FLASH_AVL_MEM_NUMBER_OF_SECTORS 1024
+#define EXT_FLASH_AVL_MEM_PAGE_SIZE 256
+#define EXT_FLASH_AVL_MEM_SECTOR_SIZE 65536
+#define EXT_FLASH_AVL_MEM_SPAN 67108864
+#define EXT_FLASH_AVL_MEM_SUBSECTOR_SIZE 4096
+#define EXT_FLASH_AVL_MEM_TYPE "altera_generic_quad_spi_controller2"
+
+
/*
* hal configuration
*
@@ -217,6 +263,23 @@
#define ALT_TIMESTAMP_CLK none
+/*
+ * i2c_0 configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_i2c_0 altera_avalon_i2c
+#define I2C_0_BASE 0x100200
+#define I2C_0_FIFO_DEPTH 16
+#define I2C_0_FREQ 50000000
+#define I2C_0_IRQ 4
+#define I2C_0_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define I2C_0_NAME "/dev/i2c_0"
+#define I2C_0_SPAN 64
+#define I2C_0_TYPE "altera_avalon_i2c"
+#define I2C_0_USE_AV_ST 0
+
+
/*
* jtag_uart_0 configuration
*
@@ -235,6 +298,109 @@
#define JTAG_UART_0_WRITE_THRESHOLD 8
+/*
+ * led configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_led altera_avalon_pio
+#define LED_BASE 0x1002e0
+#define LED_BIT_CLEARING_EDGE_REGISTER 0
+#define LED_BIT_MODIFYING_OUTPUT_REGISTER 0
+#define LED_CAPTURE 0
+#define LED_DATA_WIDTH 4
+#define LED_DO_TEST_BENCH_WIRING 0
+#define LED_DRIVEN_SIM_VALUE 0
+#define LED_EDGE_TYPE "NONE"
+#define LED_FREQ 50000000
+#define LED_HAS_IN 0
+#define LED_HAS_OUT 1
+#define LED_HAS_TRI 0
+#define LED_IRQ -1
+#define LED_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define LED_IRQ_TYPE "NONE"
+#define LED_NAME "/dev/led"
+#define LED_RESET_VALUE 0
+#define LED_SPAN 16
+#define LED_TYPE "altera_avalon_pio"
+
+
+/*
+ * msgdma_0_csr configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_0_csr altera_msgdma
+#define MSGDMA_0_CSR_BASE 0x1002c0
+#define MSGDMA_0_CSR_BURST_ENABLE 1
+#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 1
+#define MSGDMA_0_CSR_CHANNEL_ENABLE 0
+#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_0_CSR_CHANNEL_WIDTH 8
+#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32
+#define MSGDMA_0_CSR_DATA_WIDTH 32
+#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128
+#define MSGDMA_0_CSR_DMA_MODE 0
+#define MSGDMA_0_CSR_ENHANCED_FEATURES 0
+#define MSGDMA_0_CSR_ERROR_ENABLE 0
+#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
+#define MSGDMA_0_CSR_ERROR_WIDTH 8
+#define MSGDMA_0_CSR_IRQ 3
+#define MSGDMA_0_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define MSGDMA_0_CSR_MAX_BURST_COUNT 2
+#define MSGDMA_0_CSR_MAX_BYTE 1024
+#define MSGDMA_0_CSR_MAX_STRIDE 1
+#define MSGDMA_0_CSR_NAME "/dev/msgdma_0_csr"
+#define MSGDMA_0_CSR_PACKET_ENABLE 0
+#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
+#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
+#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_0_CSR_RESPONSE_PORT 2
+#define MSGDMA_0_CSR_SPAN 32
+#define MSGDMA_0_CSR_STRIDE_ENABLE 0
+#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_0_CSR_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_0_CSR_TYPE "altera_msgdma"
+
+
+/*
+ * msgdma_0_descriptor_slave configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_msgdma_0_descriptor_slave altera_msgdma
+#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x1002f0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 1
+#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 1
+#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8
+#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32
+#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32
+#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128
+#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8
+#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ -1
+#define MSGDMA_0_DESCRIPTOR_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2
+#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024
+#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1
+#define MSGDMA_0_DESCRIPTOR_SLAVE_NAME "/dev/msgdma_0_descriptor_slave"
+#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2
+#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16
+#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
+#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE "Aligned Accesses"
+#define MSGDMA_0_DESCRIPTOR_SLAVE_TYPE "altera_msgdma"
+
+
/*
* onchip_flash_0_csr configuration
*
@@ -320,12 +486,59 @@
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
-#define ONCHIP_MEMORY2_0_SIZE_VALUE 167936
-#define ONCHIP_MEMORY2_0_SPAN 167936
+#define ONCHIP_MEMORY2_0_SIZE_VALUE 131072
+#define ONCHIP_MEMORY2_0_SPAN 131072
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1
+/*
+ * spi_0 configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
+#define SPI_0_BASE 0x100280
+#define SPI_0_CLOCKMULT 1
+#define SPI_0_CLOCKPHASE 1
+#define SPI_0_CLOCKPOLARITY 0
+#define SPI_0_CLOCKUNITS "Hz"
+#define SPI_0_DATABITS 8
+#define SPI_0_DATAWIDTH 16
+#define SPI_0_DELAYMULT "1.0E-9"
+#define SPI_0_DELAYUNITS "ns"
+#define SPI_0_EXTRADELAY 0
+#define SPI_0_INSERT_SYNC 0
+#define SPI_0_IRQ 5
+#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define SPI_0_ISMASTER 1
+#define SPI_0_LSBFIRST 0
+#define SPI_0_NAME "/dev/spi_0"
+#define SPI_0_NUMSLAVES 1
+#define SPI_0_PREFIX "spi_"
+#define SPI_0_SPAN 32
+#define SPI_0_SYNC_REG_DEPTH 2
+#define SPI_0_TARGETCLOCK 128000u
+#define SPI_0_TARGETSSDELAY "0.0"
+#define SPI_0_TYPE "altera_avalon_spi"
+
+
+/*
+ * sysid configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
+#define SYSID_BASE 0x100300
+#define SYSID_ID 0
+#define SYSID_IRQ -1
+#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
+#define SYSID_NAME "/dev/sysid"
+#define SYSID_SPAN 8
+#define SYSID_TIMESTAMP 1512455752
+#define SYSID_TYPE "altera_avalon_sysid_qsys"
+
+
/*
* timer_0 configuration
*
@@ -333,7 +546,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
-#define TIMER_0_BASE 0x440200
+#define TIMER_0_BASE 0x1002a0
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 50000000